PA28F800BVT70 Datasheet PDF - Intel Corporation
| Part Number | PA28F800BVT70 | |
| Description | 8-MBIT (512K X 16/ 1024K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY | |
| Manufacturers | Intel Corporation | |
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There is a preview and PA28F800BVT70 download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
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E
PRODUCT PREVIEW
8-MBIT (512K X 16, 1024K X 8)
SmartVoltage BOOT BLOCK
FLASH MEMORY FAMILY
28F800BV-T/B, 28F800CV-T/B, 28F008BV-T/B
28F800CE-T/B, 28F008BE-T/B
Intel SmartVoltage Technology
5V or 12V Program/Erase
2.7V, 3.3V or 5V Read Operation
Program Time Reduced 60% at
12V VPP
Very High Performance Read
5V: 70/120 ns Max. Access Time,
30/40 ns Max. Output Enable Time
3V: 120/150 ns Max Access
65 ns Max. Output Enable Time
2.7V: 120 ns Max Access
65 ns Max. Output Enable Time
Low Power Consumption
Max 60 mA Read Current at 5V
Max 30 mA Read Current at 2.7–3.6V
x8/x16-Selectable Input/Output Bus
28F800 for High Performance 16- or
32-bit CPUs
x8-Only Input/Output Architecture
28F008B for Space-Constrained
8-bit Applications
Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
Seven 128-KB Main Blocks
Top or Bottom Boot Locations
Absolute Hardware-Protection for Boot
Block
Software EEPROM Emulation with
Parameter Blocks
Extended Temperature Operation
–40°C to +85°C
Extended Cycling Capability
100,000 Block Erase Cycles
(Commercial Temperature)
10,000 Block Erase Cycles
(Extended Temperature)
Automated Word/Byte Write and Block
Erase
Industry-Standard Command User
Interface
Status Registers
Erase Suspend Capability
SRAM-Compatible Write Interface
Automatic Power Savings Feature
1 mA Typical ICC Active Current in
Static Operation
Reset/Deep Power-Down Input
0.2 µA ICCTypical
Provides Reset for Boot Operations
Hardware Data Protection Feature
Erase/Write Lockout during Power
Transitions
Industry-Standard Surface Mount
Packaging
40-Lead TSOP
44-Lead PSOP: JEDEC ROM
Compatible
48-Lead TSOP
Footprint Upgradeable from 2-Mbit and
4-Mbit Boot Block Flash Memories
ETOX™ IV Flash Technology
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION 1995
September 1995
Order Number: 290539-002
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E
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
1.2 Main Features
Intel’s SmartVoltage technology is the most
flexible voltage solution in the flash
industry, providing two discrete voltage
supply pins: VCC for read operation, and VPP
for program and erase operation. Discrete
supply pins allow system designers to use
the optimal voltage levels for their design.
All products (28F800BV/CV, 28F008BV,
28F800CE and 28F008BE) provide
program/erase capability at 5V or 12V. The
28F800BV/CV and 28F008BV allows reads
with VCC at 3.3 ± 0.3V or 5V, while the
28F800CE and 28F008BE allows reads
with VCC at 2.7–3.6V or 5V. Since many
designs read from the flash memory a large
percentage of the time, 2.7V VCC operation
can provide great power savings. If read
performance is an issue, however, 5V VCC
provides faster read access times. For
program and erase operations, 5V VPP
operation eliminates the need for in system
voltage converters, while 12V VPP operation
provides faster program and erase for
situations where 12V is available, such as
manufacturing or designs where 12V is in-
system. For design simplicity, however, just
hook up VCC and VPP to the same 5V ± 10%
source.
The 28F800/28F008B boot block flash
memory family is a high-performance,
8-Mbit (8,388,608 bit) flash memory family
organized as either
512 Kwords of 16 bits each (28F800 only)
or
1024 Kbytes of 8 bits each (28F800 and
28F008B).
Separately erasable blocks, including a
hardware-lockable boot block (16,384
bytes), two parameter blocks (8,192 bytes
each) and main blocks (one block of 98,304
bytes and seven blocks of 131,072 bytes)
define the boot block flash family
PRODUCT PREVIEW
architecture. See Figures 4 and 5 for
memory maps. Each block can be
independently erased and programmed
100,000 times at commercial temperature or
10,000 times at extended temperature.
The boot block is located at either the top
(denoted by -T suffix) or the bottom (-B
suffix) of the address map in order to
accommodate different microprocessor
protocols for boot code location. The
hardware-lockable boot block provides
complete code security for the kernel code
required for system initialization. Locking
and unlocking of the boot block is
controlled by WP# and/or RP# (see Section
3.4 for details).
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ PA28F800BVT70.PDF Datasheet ] | |
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