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PDF P87CL881H Data sheet ( Hoja de datos )
| Número de pieza | P87CL881H | |
| Descripción | Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
P87CL881H
Low-voltage microcontroller with
63-kbyte OTP program memory
and 2-kbyte RAM
Product specification
File under Integrated Circuits, IC17
1999 Apr 16
1 page  
Philips Semiconductors
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
5 PINNING INFORMATION
5.1 Pinning
Product specification
P87CL881H
handbook, full pagewidth
P1.5/INT7 1
P1.6/INT8/SCL 2
P1.7/INT9/SDA 3
RST 4
P3.0/RXD/data 5
PORENABLE/VPP 6
P3.1/TXD/clock 7
P3.2/INT0 8
P3.3/INT1 9
P3.4/T0 10
P3.5/T1 11
P87CL881H
33 P0.4/AD4
32 P0.5/AD5
31 P0.6/AD6
30 P0.7/AD7
29 EA
28 EW
27 ALE
26 PSEN
25 P2.7/A15
24 P2.6/A14
23 P2.5/A13
MGL616
1999 Apr 16
Fig.2 Pin configuration.
5
5 Page 
Philips Semiconductors
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
Product specification
P87CL881H
Mode 1 Standard port; quasi-bidirectional I/O with
pull-up. The strong pull-up p1 is turned on for
only one oscillator periods after a LOW-to-HIGH
transition in the port latch. After these two
oscillator periods the port is only weakly driven
through p2 and ‘very weakly’ driven through p3.
See Fig.3b.
Mode 2 High-impedance; this mode turns all port output
drivers off. Thus, the pin will not source or sink
current and may be used as an input-only pin with
no internal drivers for an external device to
overcome. See Fig.3c.
Mode 3 Push-pull; output with drive capability in both
polarities. In this mode, pins can only be used as
outputs. See Fig.3d.
Tables 2 and 3 show the configuration register settings for
the four output configurations. The electrical
characteristics of each output configuration are specified
in Chapter 8. The default port configuration after reset is
given in Table 2.
In case of external memory access, the appropriate
options for ports P0, P2 and P3.6/P3.7 (WR/RD, only in
case of external data memory access) must be set by
software.
For Special Function Registers for port configurations/data
please refer to Table 2, note 1.
Table 3 Port configuration register settings
MODE(1)
0
1
2
3
PnCFGA
0
1
0
1
PnCFGB
PORT OUTPUT CONFIGURATION
NORMAL PORTS
I2C-BUS PORTS (P1.6 AND P1.7)
0 open-drain
open-drain
0 quasi-bidirectional
open-drain
1 high-impedance
high-impedance
1 push-pull
open-drain
Note
1. Mode changes may cause glitches to occur during transitions. When modifying both registers, write instructions
should be carried out consecutively.
1999 Apr 16
11
11 Page | ||
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