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PDF P87C51RC2 Data sheet ( Hoja de datos )
| Número de pieza | P87C51RC2 | |
| Descripción | 80C51 8-bit microcontroller family | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
P87C51RA2/RB2/RC2/RD2
80C51 8-bit microcontroller family
8KB/16KB/32KB/64KB OTP, 512B/512B/512B/1KB RAM,
low voltage (2.7 to 5.5 V), low power, high speed
(30/33 MHz)
Product data
Supersedes data of 2002 Oct 28
2003 Jan 24
Philips
Semiconductors
1 page  
Philips Semiconductors
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
Product data
P87C51RA2/RB2/RC2/RD2
BLOCK DIAGRAM (CPU-ORIENTED)
VCC
VSS
RAM ADDR
REGISTER
RAM
P0.0–P0.7
PORT 0
DRIVERS
PORT 0
LATCH
P2.0–P2.7
PORT 2
DRIVERS
PORT 2
LATCH
OTP
MEMORY
B
REGISTER
ACC
TMP2
TMP1
STACK
POINTER
8
PROGRAM
ADDRESS
REGISTER
ALU
PSW
PSEN
ALE
EAVPP
RST
TIMING
AND
CONTROL
PD
OSCILLATOR
XTAL1
XTAL2
PORT 1
LATCH
PORT 1
DRIVERS
P1.0–P1.7
SFRs
TIMERS
P.C.A.
PORT 3
LATCH
BUFFER
PC
INCRE-
MENTER
8
PROGRAM
COUNTER
DPTR’S
MULTIPLE
PORT 3
DRIVERS
P3.0–P3.7
16
SU01658
2003 Jan 24
5
5 Page 
Philips Semiconductors
80C51 8-bit microcontroller family 8KB/16KB/32KB/64KB OTP
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
Product data
P87C51RA2/RB2/RC2/RD2
CLOCK CONTROL REGISTER (CKCON)
This device allows control of the 6-clock/12-clock mode by means of
both an SFR bit (X2) and an OTP bit. The OTP clock control bit
OX2, when programmed (6-clock mode), supersedes the X2 bit
(CKCON.0). The CKCON register is shown below in Figure 1.
CKCON Address = 8Fh
Not Bit Addressable
Reset Value = x0000000B
76543210
– – – – – – – X2
BIT
CKCON.7
CKCON.6
CKCON.5
CKCON.4
CKCON.3
CKCON.2
CKCON.1
CKCON.0
SYMBOL
–
X2
FUNCTION
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
CPU clock; 1 = 6 clocks for each machine cycle, 0 = 12 clocks for each machine cycle
SU01689
Figure 1. Clock control (CKCON) register
Also please note that the clock divider applies to the serial port for
modes 0 & 2 (fixed baud rate modes). This is because modes 1 & 3
(variable baud rate modes) use either Timer 1 or Timer 2.
Below is the truth table for the CPU clock mode.
Table 1.
OX2 clock mode bit
(can only be set by
parallel programmer)
X2 bit
(CKCON.0)
CPU clock mode
erased
0 12-clock mode
(default)
erased
1 6-clock mode
programmed
X
6-clock mode
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (12 oscillator periods in 6-clock mode, or 24 oscillator
periods in 12-clock mode), while the oscillator is running. To ensure a
good power-on reset, the RST pin must be high long enough to allow
the oscillator time to start up (normally a few milliseconds) plus two
machine cycles. At power-on, the voltage on VCC and RST must
come up at the same time for a proper start-up. Ports 1, 2, and 3 will
asynchronously be driven to their reset condition when a voltage
above VIH1 (min.) is applied to RST.
The value on the EA pin is latched when RST is deasserted and has
no further effect.
2003 Jan 24
11
11 Page | ||
| Páginas | Total 67 Páginas | |
| PDF Descargar | [ Datasheet P87C51RC2.PDF ] | |
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