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PDF TH6503 Data sheet ( Hoja de datos )
| Número de pieza | TH6503 | |
| Descripción | USB Low-Speed Interface | |
| Fabricantes | ETC | |
| Logotipo |  |
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TH6503
USB Low-Speed Interface
Description
The TH6503 is an integrated circuit which enables
the Universal Serial Bus (USB) to be connected to
a microcontroller. The interface module contains
all the components required to transmit data via
the USB.
The TH6503 has been developed for applications
requiring a low speed interface to the USB. Any
microcontroller can be used for control purposes.
In addition to the default endpoint 0 for control
transfer up to two endpoints can be supported by
TH6503. The TH6503 has been developed in
conformity with USB Specifications 1.1.
Features
? Complient with USB Specification 1.1
? Provides power supply for the microcontroller
? Supports up to three programmable endpoints
(3.3 volts or 5 volts)
for interrupt and control transfer in each direction ? Integrated oscillator for clock generation,
? Data transfer at USB low speed
? Supports suspend mode
? Universal serial microcontroller interface
supports 6 MHz quartz, ceramic resonator
or external clock input
? Simple external circuitry
? Register programmable
? Programmable 1.5 MHz to 6 MHz out clock for
microcontroller
TH6503 Sample
Application
TH6503
to USB
Host / Hub
Serial
Interface
USB
Interface
OCLK
/ORST
Micro-
controller/
Customer
Application
Figure 1. Typical TH6503 Sample Application
Figure 1 demonstrates a typical TH6503 applica-
tion. The TH6503 translates the data and control
signals received from the USB in a serial format
which can be read by the microcontroller. The data
is stored in a FIFO buffer and can be called up from
a standard microcontroller via a register program-
mable serial interface at any time and processed
further. Data generated by peripheries is passed
to the TH6503 with the same protocol and stored
in a FIFO buffer until it is collected by the USB. The
TH6503 translates all the data in the USB-specific
format and generates the necessary control sig-
nals. The TH6503 requires a minimum number of
external elements and can easily be implemented
in a circuitry. It provides an external clock which
can be used to activate a microcontroller.
Rev. 3.5
Dec 2000
1 page  
TH6503 USB Low-Speed Interface
Microcontroller
Interface
(continued)
1
SCK
0
Microcontroller
latches Data
on rising edge
of SCK
0
Bridge shifts
Data on falling
edge of SCK
1
1
SIN
0
1
SDO
0
1
SDI
0
Status0
Status1 Status2
Clear Interrupt Latch
SDI pulse with SIN=0:
- transfer StatusRegister to Serial Data Out
7 15
Bridge outputs
next Register (CntOutRegister)
Bit 0 on SDO
n+16
End of OUT Transfer
(OUT Tranfer after reading
the Status -and CntOutRegister
with SIN=0 clears
EP0 Out Done
Status7 CNT0
CNT7 FIFO Bit 0
Bit n
/INT
Figure 6. Complete Data OUT Transfer
1
SCK
0
1
SIN
0
1
SDO
0
1
SDI
0
Microcontroller
latches Data
on rising edge
of SCK
0
Bridge shifts
Data on falling
edge of SCK
CNT0
CNT1
Two SDI pulses with SIN=0:
- transfer CntOutRegister and OUT FIFO Bytes
to Serial Data Out
7
Bridge outputs
next Register (FIFO)
Bit 0 on SDO
End of OUT Transfer
(OUT Tranfer > 8 clocks
the Status -and CntOutRegister
with SIN=0 clears
EP0 Out Done
n+8
CNT7 FIFO Bit 0
Bit n
/INT
Figure 7. OUT Transfer, only CntOutRegister and OUT FIFO Bytes
Interrupt Function
If SIN = 1, the SDO pin can be used to generate an
interrupt signal. The interrupt is low active. It is
triggered if a control transfer is made from the USB
host or a control or interrupt transfer is made to the
USB host and one of the ID12, ID0 or OD bits has
been set in the StatusRegister <3-1> or at high
level of the WAKE pin. An interrupt signal is also
triggered on RESUME and USB_RESET.
The interrupt latch is reset on reading the status
register. If an interrupt is generated during read-
ing StatusRegister, this interrupt is latched and
the interrupt source is after new StatusRegister
reading visible.
A WAKE interrupt is only generated during the stop
state (bits SO and/or SMC in the BridgeConfig
Register are set).
5
5 Page 
TH6503 USB Low-Speed Interface
Register
Description
(continued)
CntOutRegister (read only)
second byte of each out transfer following an OUT packet sync
Bit Bit
Number Mnemonic
7-6 OA
Reset
Status
0
5 TO 0
4 SET 0
3-0 OC3-0
0
Function
OUT Address
last valid OUT endpoint
? indicates the endpoint of actual OUT FIFO data
00 EP0
01 EP1
10 EP2
? only valid if EP1 OUT or EP2 OUT enabled, otherwise the internal
Revision number is visible
Toggle OUT
? is set if the data packet PID was DATA1 and reset if the data packet
PID was DATA0
? is latched with a valid EP0 SETUP or a OUT Token
Setup
? is set if a SETUP token is received
? is reset after OUT transfer to microcontroller
? no STALL or NAK is sent because it is not permitted on the SETUP
token
? the SO0 and SI0 (STALL EP0) flags in the USBFlagRegister are reset
on rising edge of Setup
? a SETUP token flash all IN FIFOs
EP0 OUT Byte Count
amount of OUT data received in the EP0 FIFO in bytes
? applicable values from 0 to 8
? a zero data transfer is identified 0
Internal Register
Adr/CntInRegister (write only)
first byte of each data in transfer following the IN packet sync
Bit
Number
7
Bit
Mnemonic
TI
6-4 RA2-0
3-0 IC3-0
Reset
Status
0
0
0
Function
Toggle IN
? is set if the data packet PID is DATA1 and reset if the data packet PID
is DATA0
Internal Address
destination address for a write operation to a TH6503 register or IN
FIIFO
IN Byte Count
number of data bytes to be transmitted without Adr/CntInRegister from
the microcontroller to the TH6503 if the destination address was an IN
FIFO
? applicable values from 0 to 8
? 0 indicates a zero data transfer to the USB host, but blocks the InFIFO
until ACK is received
11
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