PDF P82B96T Data sheet ( Hoja de datos )

Número de pieza	P82B96T
Descripción	Dual bi-directional bus buffer
Fabricantes	NXP Semiconductors
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INTEGRATED CIRCUITS P82B96 Dual bi-directional bus buffer Product data Supersedes data of 2003 Apr 02 2004 Mar 26 Philips Semiconductors 1 page Philips Semiconductors Dual bi-directional bus buffer Product data P82B96 SYMBOL PARAMETER ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁInput logic switching threshold voltages ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVSx, VSy Input logic voltage LOW (Note 3) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVSx, VSy Input logic level HIGH threshold (Note 3) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁdVSx/dT, ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁdVSy/dT Temperature coefficient of input thresholds ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVRx, VRy Input logic HIGH level VRx, VRy Input threshold ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVRx, VRy Input logic LOW level ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁLogic level threshold difference ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVSx, VSy Input/Output logic level difference (Note 1) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁNOTES: CONDITIONS On normal I2C-bus On normal I2C-bus Fraction of applied VCC Fraction of applied VCC Fraction of applied VCC VSX output LOW at 0.2 mA – VSX input HIGH max MIN. TYP. MAX. UNIT — 640 600 mV 700 650 — mV — –2 — mV/K 0.58 — — — 0.5 — — — 0.42 V V V 50 85 — mV 1. The minimum value requirement for pull-up current, 200 µA, guarantees that the minimum value for VSX output LOW will always exceed the minimum VSX input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC. While the tolerances on absolute levels allow a small probability the LOW from one SX output is recognized by an SX input of another P82B96 this has no consequences for normal applications. In any design the SX pins of different ICs should never be linked because the resulting system would be very susceptible to induced noise and would not support all I2C operating modes. 2. The output logic LOW depends on the sink current. For scaling, see Application Note AN255. 3. The input logic threshold is independent of the supply voltage. CHARACTERISTICS At Tamb = 25 °C; Voltages are specified with respect to GND with VCC = 5 V unless otherwise stated. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁSYMBOL PARAMETER CONDITIONS MIN. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁBus Release on VCC Failure ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVSx, VSy, ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVTx, VTy VCC voltage at which all buses are guaranteed to be released ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁdV/dT Temperature coefficient of guaranteed release voltage — — ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁBuffer response time ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁTfall delay ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVSx to VTx VSy to VTy ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁTrise delay ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVSx to VTx VSy to VTy ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁTfall delay ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVRx to VSx ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVRy to VSy ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁTrise delay VRx to VSx ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVRy to VSy Buffer time delay on FALLING input between VSx = input switching threshold, and VTx output falling 50%. Buffer time delay on RISING input between VSx = input switching threshold, and VTx output reaching 50% VCC Buffer time delay on FALLING input between VRx = input switching threshold, and VSx output falling 50%. Buffer time delay on RISING input between VRx = input switching threshold, and VSx output reaching 50% VCC RTx pull-up = 160 Ω, no capacitive load, VCC = 5 V RTx pull-up = 160 Ω, no capacitive load, VCC = 5 V RSx pull-up = 1500 Ω, no capacitive load, VCC = 5 V RSx pull-up = 1500 Ω, no capacitive load, VCC = 5 V — — — — ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁInput capacitance ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁCin Effective input capacitance of any signal pin ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁmeasured by incremental bus rise times — TYP. MAX. UNIT — 1V –4 — mV/K 70 — ns 90 — ns 250 — ns 270 — ns — 7 pF NOTES ON RESPONSE TIME The fall-time of VTX from 5 V to 2.5 V in the test is approximately 15 ns. The fall-time of VSX from 5 V to 2.5 V in the test is approximately 50 ns. The rise-time of VTX from 0 V to 2.5 V in the test is approximately 20 ns. The rise-time of VSX from 0.9 V to 2.5 V in the test is approximately 70 ns. 2004 Mar 26 5 5 Page Philips Semiconductors Dual bi-directional bus buffer Product data P82B96 12 V 3.3–5 V SCL SX TX RX 3.3–5 V SDA SY TY RY P82B96 ch1: freq = 624 kHz 12 V TWISTED-PAIR TELEPHONE WIRES, USB, OR FLAT RIBBON CABLES. UP TO 15 V LOGIC LEVELS, INCLUDE VCC AND GND. 12 V 3.3 V 3.3 V P82B96 P82B96 P82B96 SX SY SX SY SX SY SCL/SDA SCL/SDA SCL/SDA NO LIMIT TO THE NUMBER OF CONNECTED BUS DEVICES. P82B96 Figure 9. I2C multi-point applications SY SDA SX SCL su01709 Tx 10 V Sx 5 V ch1: freq = 624 kHz Rx Sx CH1!2.00V = AVG CH2!2.00V = BWL MTB 200 ns – 0.98dvch1+ 0V Horiz: 200 ns/div. VertL 2 V/div. SU01069 Figure 10. Propagation Sx to Tx — Sx pull-up to 5V, Tx pull-up to VCC = 10 V CH1!2.00V = AVG CH2!2.00V = BWL MTB 200 ns – 0.98dvch1+ Horiz: 200 ns/div. VertL 2 V/div. SU01070 Figure 11. Propagation Rx to Sx — Sx pull-up to 5V, Rx pull-up to VCC = 10 V 2004 Mar 26 11 11 Page

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