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PDF TGA8035 Data sheet ( Hoja de datos )
| Número de pieza | TGA8035 | |
| Descripción | Gain Block Amplifier | |
| Fabricantes | TriQuint Semiconductor | |
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T R I Q U I N T S E M I C ON D U C TO R, I N C.
TGA8035-SCC
8035Gain Block Amplifier
q 6 to 18-GHz Frequency Range
q 13-dB Typical Gain
q 2.2:1 Typical Input/Output SWR
q 12.5-dBm Typical Output Power at 1 -dB Gain Compression
q 5-dB Typical Noise Figure
q 2,4892 x 2,0574 x 0,1143 mm (0.098 x 0.081 x 0.0045 in.)
PHOTO ENLARGEMENT
DESCRIPTION
The TriQuint TGA8035 - SCC is a two - stage GaAs monolithic amplifier designed for use as
a broadband general-purpose gain block. T wo 300 - µm gate - width FETs provide a 13- dB typical gain and
a 5- dB noise figure from 6 to 18- GHz. Typical output power at 1- dB gain compression is 12.5- dBm.
Shunt feedback is used around each active device to improve gain flatness and standing - wave ratio
(SWR). Ground is provided to the circuitry through vias to the backside metallization.
The TGA8035-SCC amplifier is suitable for a variety of broadband electronic warfare (EW) applications.
The combination of gain, power, and noise figure makes this device an exceptional post amplifier
following a low-noise amplifier.
Bond pad and backside metallization is gold plated for compatibility with eutectic alloy attachment
methods as well as thermocompression and thermosonic wire- bonding processes. The TGA8035 - SCC
is supplied in chip form and is readily assembled using automated equipment.
TriQuint Semiconductor, Inc. • Texas Facilities • (972) 995-8465 • www.triquint.com
1 page  
TGA8035-SCC
RF CHARACTERISTICS
GP
SWR(in)
SWR(out)
P 1dB
NF
PARAMETER
Small–signal power gain
Input standing–wave ratio
Output standing–wave ratio
Output power at 1–dB gain compression
Noise figure
TEST CONDITIONS
f = 6 to 18 G Hz
f = 6 to 18 GHz
f = 6 to 18 G Hz
f = 6 to 18 G Hz
f = 6 to 18 GHz
VD1, VD2 = 5 V, VG1 = - 1 V, VG2 = - 1 V, TA = 25°C
TYP UNIT
13 dB
2.2:1 —
2.2:1 —
12.5 dBm
5 dB
DC CHARACTERISTICS
PARAMETER
I DSS1 Total zero–gate–voltage drain current at saturation
for FET1 *
I DSS2 Total zero–gate–voltage drain current at saturation
for FET2 **
TEST CONDITIONS
V DS = 0.5 V to 3.5 V,
VGS = 0
V DS = 0.5 V to 3.5 V,
V GS = 0
MIN MAX UNIT
36 108 mA
36 108 mA
TA = 25°C
* VDS1 for IDSS1 is drain voltage between 0.5 V and 3.5 V at which drain current is highest at DC autoprobe.
** VDS2 for IDSS2 is drain voltage between 0.5 V and 3.5 V at which drain current is highest at DC autoprobe.
THERMAL INFORMATION
PARAMETER
R JC Thermal resistance,
channel–to–backside
TEST CONDITIONS
ID=72 mA, V D=5V
TEST CONDITIONS
25°C Base, 80°C Channel**
85°C Base, 151°C Channel**
100°C Base, 169°C Channel**
F ET MMIC* UNIT
152.5 76.3
184.7 92.4 °C/W
192.8 96.4
* MMIC thermal resistance is the peak FET temperature rise divided by the total MMIC dissipated power (.72 W).
** Hottest Gate Channel (Center of either FET).
EQUIVALENT
SCHEMATIC
RF Input
VG1
RF Output
FET 2
300 m
V
D2
FET 1
300 m
V D1
VG2
TriQuint Semiconductor, Inc. • Texas Facilities • (972) 995-8465 • www.triquint.com
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet TGA8035.PDF ] | |
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