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Número de pieza | TDA9855 | |
Descripción | I2C-bus controlled BTSC stereo/SAP decoder and audio processor | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de TDA9855 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! INTEGRATED CIRCUITS
DATA SHEET
TDA9855
I2C-bus controlled BTSC
stereo/SAP decoder and audio
processor
Product specification
Supersedes data of July 1994
File under Integrated Circuits, IC02
1997 Nov 04
1 page Philips Semiconductors
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
Product specification
TDA9855
Component list
Electrolytic capacitors ±20%; foil or ceramic capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1.
COMPONENTS
VALUE
TYPE
REMARK
C1
10 µF
electrolytic
63 V
C2 470 nF foil
−
C3
4.7 µF
electrolytic
63 V
C4 220 nF foil
−
C5
10 µF
electrolytic
63 V; Ileak < 1.5 µA
C6
2.2 µF
electrolytic
16 V
C7
4.7 µF
electrolytic
16 V
C8 15 nF foil
±5%
C9 15 nF foil
±5%
C10
2.2 µF
electrolytic
63 V
C11
8.2 nF
foil or ceramic
±5% SMD 2220/1206
C12 150 nF
foil
±5%
C13 33 nF
foil
±5%
C14
5.6 nF
foil or ceramic
±5% SMD 2220/1206
C15
100 µF
electrolytic
16 V
C16
4.7 µF
electrolytic
63 V
C17
4.7 µF
electrolytic
63 V
C18 100 nF
foil
C19
10 µF
electrolytic
63 V
C20
4.7 µF
electrolytic
63 V
C21 47 nF
foil
±5%
C22
1 µF
electrolytic
63 V
C23
1 µF
electrolytic
63 V
C24
10 µF
electrolytic
63 V ±10%
C25
10 µF
electrolytic
63 V ±10%
C26
2.2 µF
electrolytic
16 V
C27
2.2 µF
electrolytic
63 V
C28
4.7 µF
electrolytic
63 V ±10%
C29
2.2 µF
electrolytic
16 V
C30
8.2 nF
foil or ceramic
±5% SMD 2220/1206
C31 150 nF
foil
±5%
C32 33 nF
foil
±5%
C33
5.6 nF
foil or ceramic
±5% SMD 2220/1206
C34
100 µF
electrolytic
16 V
C35 150 nF
foil
±5%
C36
4.7 µF
electrolytic
16 V
C37
4.7 µF
electrolytic
16 V
C39
4.7 µF
electrolytic
16 V
C40
4.7 µF
electrolytic
16 V
1997 Nov 04
5
5 Page Philips Semiconductors
I2C-bus controlled BTSC stereo/SAP
decoder and audio processor
Product specification
TDA9855
SUBWOOFER; SURROUND SOUND CONTROL
The subwoofer or the surround mode can be activated with
the control bit SUR (see Table 6). A low bit provides an
output signal 1⁄2(L + R) in subwoofer mode, a high bit
selects surround mode and provides an output signal
1⁄2(L − R). The signal is fed through a volume control stage
with a range from +14 to −14 dB in 2 dB steps on top of the
main channel control to the output pin OUTS. The last
setting is the mute position (see Table 11). The capacitor
C35 at pin SW provides a 230 Hz low-pass filter in
subwoofer mode. In surround mode this capacitor should
be disconnected. If balance is not in mid position the
selected left and right output levels will be combined.
MUTE
The mute function can be activated independently with the
last step of volume or subwoofer/surround control at the
left, right or centre output. By setting the general mute bit
GMU via the I2C-bus all audio part outputs are muted.
All channels include an independent zero-crossing
detector. The zero-crossing mute feature can be selected
via bit TZCM:
TZCM = 0: forced mute with direct execution
TZCM = 1: execution in time with signal zero-crossing.
In the zero-crossing mode a change of the GMU bit is
activated but not executed. The execution is enabled at
the next zero-crossing of the signal. To avoid a large delay
of mute switching, when very low frequencies are
processed, or the output signal amplitude is lower than the
DC offset voltage, the following I2C-bus transmissions are
needed:
A first transmission for mute execution
A second transmission approximately 100 ms later,
which must switch the zero-crossing mode to forced
mute (TZCM = 0)
A third transmission to reactivate the zero-crossing
mode (TZCM = 1). This transmission can take place
immediately, but must follow before the next mute
execution.
Adjustment procedure
COMPOSITE INPUT LEVEL ADJUSTMENT
Apply the composite signal (from the FM demodulator)
with 100% modulation (25 kHz deviation) L + R;
fi = 300 Hz. Set input level control via the I2C-bus
monitoring line output (500 mV ±20 mV). Store the setting
in a non-volatile memory. Adjustment of the spectral and
wideband expander is performed via the stereo channel
separation adjust.
AUTOMATIC ADJUSTMENT PROCEDURE
• Capacitors of external inputs EIL and EIR must be
grounded
• Composite input signal L = 300 Hz, R = 3.1 kHz,
14% modulation for each channel; volume gain +16 dB
via the I2C-bus; to avoid annoying sound level set GMU
bit to logic 1 during adjustment procedure
• Effects, AVL, loudness off
• Selector setting SC0, SC1 and SC2 = 0, 0, 0
(see Table 12)
• Line out setting bits: STEREO = 1, SAP = 0
(see Table 21)
• Start adjustment by transmission ADJ = 1 in register
ALI3; the decoder will align itself
• After 1 second, stop alignment by transmitting ADJ = 0
in register ALI3 read the alignment data by an I2C-bus
read operation from ALR1 and ALR2
(see Chapter “I2C-bus protocol”) and store it in a
non-volatile memory; the alignment procedure
overwrites the previous data stored in ALI1 and ALI2
• Disconnect the capacitors of external inputs from
ground.
MANUAL ADJUSTMENT
Manual adjustment is necessary when no dual tone
generator is available (e.g. for service).
• Spectral and wideband data have to be set to 10000
(middle position for adjustment range)
• Composite input L = 300 Hz; 14% modulation
• Adjust channel separation by varying wideband data
• Composite input L = 3 kHz; 14% modulation
• Adjust channel separation by varying spectral data
• Iterative spectral/wideband operation for optimum
adjustment
• Store data in non-volatile memory.
After every power-on, the alignment data and the input
level adjustment data must be loaded from the non-volatile
memory.
TIMING CURRENT FOR RELEASE RATE
Due to possible internal and external spreading, the timing
current can be adjusted via the I2C-bus (see Table 25) as
recommended by dbx.
1997 Nov 04
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet TDA9855.PDF ] |
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