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PDF TDA9203 Data sheet ( Hoja de datos )
| Número de pieza | TDA9203 | |
| Descripción | I2C BUS CONTROLLED 70MHz RGB PREAMPLIFIER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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TDA9203A
I2C BUS CONTROLLED 70MHz RGB PREAMPLIFIER
. 70MHz TYPICAL BANDWIDTH AT 4VPP OUT-
PUT WITH 12pF CAPACITIVE LOAD
. 5.5ns TYPICAL RISE/FALL TIME AT 4VPP
OUTPUT WITH 12pF CAPACITIVE LOAD
. POWERFULL OUTPUT DRIVE CAPABILITY
. BRT, CONT, DRIVE, OUTPUT DC LEVEL,
OSD CONTRAST, BACK-PORCH CLAMPING
PULSE WIDTH ARE I2C BUS CONTROLLED
. INTERNAL BACK-PORCH CLAMPING
PULSE GENERATOR
. OSD WHITE BALANCE TRACKING
. INTERNAL OSD SWITCHES
. BLANKING AND FAST-BLANKING INPUTS
. VERY LARGE DRIVE ADJUSTMENT RANGE
(48dB)
. SEMI-TRANSPARENT BACKGROUND ON
OSD PICTURE
. ABL CONTROL
SHRINK 24
(Plastic Package)
ORDER CODE : TDA9203A
PIN CONNECTIONS
DESCRIPTION
The TDA9203A is a digitaly controlled wideband
video preamplifier intended for use in mid range
color monitor. All controls and adjustments are
digitaly performed thanks to I2C serial bus. Con-
trast, brightness and DC output level of RGB sig-
nals are common to the 3 channels and drive
adjustment is separate for each channel.Three I2C
gain controlled OSD inputs can be switched with
RGB signals using fast blanking command. Clamp-
ing of RGB signals is performed thanks to a flexible
integrated system. The white balance adjustment
is effective on brightness, video and OSD signals.
The TDA9203A works for application using AC or
DC coupled CRT driver.
The ABL input provides a 12dB Max. attenuation
on the current contrast value according average
beam limitation voltage.
Because of its features and due to component
saving the TDA9203A leads to a very performant
and cost effective application.
June 1998
IN1
OSD1
AVDD
IN2
OSD2
AGND
IN3
OSD3
ABL
LGND
SDA
SCL
1
2
3
4
5
6
7
8
9
10
11
12
24 HSYNC
23 PVCC1
22 OUT1
21 PGND1
20 PVCC2
19 OUT2
18 PGND2
17 PVCC3
16 OUT3
15 PGND3
14 BLK
13 FBLK
1/13
1 page  
TDA9203A
FUNCTIONAL DESCRIPTION (continued)
Figure 4 : Waveforms VOUT, BRT, CONT, OSD
HSYNC
BPCP
BLK
Video IN
FBLK
OSD IN
V (4)
CONT
VOUT1, VOUT2, VOUT3
V (5)
OSD
V (3)
BRT
V (2)
BLACK
V (1)
DC
OSD CONT
BRT
0.4V fixed
Notes : 1.
2.
3.
4.
5.
VDC = 0.5 to 2.5V
VBLACK = VDC + 0.4V
VBRT = VBLACK + BRT (with BRT = 0 to 2.5V)
VCONT = VBRT + CONT with CONT = k x Video IN (CONT = 5VPP max. for VIN = 0.7VPP)
VOSD = VBRT + OSD with OSD = k1 x OSDIN (OSD max. = 5.5VPP, OSD min. = 360mVPP)
Figure 5 : Waveforms (DRIVE adjustment)
HSYNC
BPCP
BLK
Video IN
FBLK
OSD IN
VOUT1, VOUT2, VOUT3
VOSD
VCONT
VBRT
VBLACK
VDC
Two exemples
of drive adjustment (1)
Note : 1. Drive adjustment modifies the following voltages : VCONT, VBRT and VOSD.
Drive adjustment do not modify the following voltages : VDC and VBLACK.
Figure 6 : I2C Write Operation
SCL
SDA
Start
I2C Slave Address
W
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
ACK
Register Address
ACK
Data Byte
ACK Stop
5/13
5 Page 
INTERNAL SCHEMATICS
Figure 8
AVDD
IN
P ins
1-4-7
AGND
Figure 10
AVDD 3
(20V)
AGND
AGND 6
Figure 12
AVDD
LGND 10
LGND
AGND
Figure 14
AVDD
HSYNC 24
AGND
LGND
Figure 9
TDA9203A
AVDD
OS D - BLK - FBLK
P ins 2-5-8-13-14
Figure 11
AGND AGND
AVDD
Internal
5V
ABL 9
10kΩ
Figure 13
AGND
S DA
SCL
P ins
11 -1 2
(10V)
AGND
Figure 15
P VC C
P ins 17-20-23
P GND
P ins 15-18-21
LGND
AVDD
OUT
Pins 16-19-22
AGND
11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet TDA9203.PDF ] | |
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