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PDF TDA9151B Data sheet ( Hoja de datos )
| Número de pieza | TDA9151B | |
| Descripción | Programmable deflection controller | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TDA9151B
Programmable deflection controller
Preliminary specification
Supersedes data of June 1993
File under Integrated Circuits, IC02
July 1994
Philips Semiconductors
1 page  
Philips Semiconductors
Programmable deflection controller
Preliminary specification
TDA9151B
PINNING
SYMBOL PIN
DESCRIPTION
HFB
1 horizontal flyback input
DSC
2 display sandcastle input/output
PROT
3 over voltage protection input
AGND
4 analog ground
LLCS
5 line-locked clock selection input
EWOUT 6 east-west geometry output
EHT
7 EHT compensation
RCONV
FLASH
8 external resistive conversion
9 flash detection input
VOUTB
VOUTA
VA
HA
LLC
10 vertical output B
11 vertical output A
12 vertical information input
13 horizontal information input
14 line-locked clock input
DGND
15 digital ground
VCC
SDA
16 supply input (+8 V)
17 serial data input/output
SCL 18 serial clock input
OFCS
19 off-centre shift output
HOUT
20 horizontal output
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Input signals (pins 12, 13, 14, 17 and 18)
The TDA9151B requires three signals for minimum
operation (apart from the supply). These signals are the
line-locked clock (LLC) and the two I2C-bus signals (SDA
and SCL). Without the LLC the device will not operate
because the internal synchronous logic uses the LLC as
the system clock.
I2C-bus transmissions are required to enable the device to
perform its required tasks. Once started the IC will use the
HA and/or VA inputs for synchronization. If the LLC is not
present the outputs will be switched off and all operations
discarded (if the LLC is not present the line drive will be
inhibited within 2 µs, the EW output current will drop to
zero and the vertical output current will drop to 20% of the
adjusted value within 100 µs). The SDA and SCL inputs
meet the I2C-bus specification, the other three inputs are
TTL compatible.
The LLC frequency can be divided-by-two internally by
connecting LLCS (pin 5) to ground thereby enabling the
prescaler.
The LLC timing is given in the Chapter “Characteristics”.
July 1994
5
5 Page 
Philips Semiconductors
Programmable deflection controller
Preliminary specification
TDA9151B
Vertical part (pins 6, 8, 10, 11 and 12)
SYNCHRONIZATION PULSE
The VA input (pin 12) is a TTL-compatible CMOS input.
Pulses at this input have to fulfil the timing requirements as
illustrated in Fig.6. For correct detection the minimum
pulse width for both the HIGH and LOW period is 2 internal
clock periods. For further requirements on minimum pulse
width see also Section “De-interlace”.
VERTICAL PLACE GENERATOR
An overview of the various modes of operation of the
vertical place generator is illustrated in Fig.13.
With control bit CPR a compress to 75% of the adjusted
values is possible in all modes of operation. This control bit
is used to display 16 : 9 standard pictures on 4 : 3
displays. No new adjustment of other corrections, such as
corner and S-correction, is required.
With control bit VPR a reduction of the current during
clipping, wait and stop modes to 20% of the nominal value
can be selected, which will reduce the dissipation in the
vertical drive circuits.
Vertical place generator in adaptive mode (MS = logic 0)
The vertical start-scan data (subaddress 02) determines
the vertical placement in the total range of 64 × 432 clock
periods in 63 steps. The maximum number of
synchronized lines per scan is 910 with an equivalent field
frequency of 17.2 or 34.4 Hz for fH = 15625 or 31250 Hz
respectively.
The minimum number of synchronized lines per scan is
200 with an equivalent field frequency of 78 or 156 Hz for
fH = 15 625 or 31250 Hz respectively.
If the VA pulse is not present, the number of lines per scan
will increase to 910.2. If the LLC is not present the vertical
blanking will start within 2 µs.
Amplitude control is automatic, with a settling time of 1 to
2 new fields and an accuracy of either 16/12 or 48/12 lines
depending on the value of the GBS bit.
Differences in the number of lines per field, as can occur in
TXT or in multi-head VTR, will not affect the amplitude
setting providing the differences are less than the value
selected with GBS. This is called amplitude control
guardband. The difference sequence and the difference
sequence length are not important.
Vertical place generator in constant slope mode
(MS = logic 1)
In this mode the slope can be programmed directly with a
two byte value on subaddress 0C (MSB) and 0D (LSB).
When the actual number of lines is greater than the
programmed number of lines, the circuit will enter the stop
state in which the differential vertical output current
remains 100% or drops to 20% (programmable with
control bit VPR). The programmed value for the slope is
the required number of lines multiplied by 72. The
programming limits are; minimum 200 × 72 and maximum
910 × 72.
A vertical expansion is obtained with a combination of
slope data and a programmable wait status, at
subaddress 0E. The wait status is selected with control bit
MS and can only be activated in the constant slope mode.
The wait state is an 8-bit value, programmable from 0 to
255. The actual wait state is one line longer than the
programmed value. If blanking is applied during stop and
wait status the differential output current will be the same
with VPR selected value (20 or 100%).
DE-INTERLACE
With de-interlace on (DINT = logic 0), the VA pulse is
sampled with LLC at a position supplied by control bit DIP
(de-interlace phase).
When DIP = logic 0 sampling takes place 42 clock pulses
after the leading edge of HA (T = Tline × 42/432).
When DIP = logic 1 sampling takes place 258 clock pulses
after the leading edge of HA (T = Tline × 258/432).
The distance between the two selectable sampling points
is (Tline × (258 − 42)/432) which is exactly half a line, thus
de-interlace is possible in two directions.
The duration of the VA pulse must, therefore, be sufficient
to enable the HA pulse to caught, in this event an active
time of minimum of half a line (see Fig.14 which has an
integration time of Tline × 1⁄4 for the VA pulse).
With de-interlace off, the VA pulse is sampled with the
system clock. The leading edge is detected and used as
the vertical reset. Selection of the positive or negative
leading edge is achieved by the control bit VAP.
July 1994
11
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