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PDF TDA9106A Data sheet ( Hoja de datos )
| Número de pieza | TDA9106A | |
| Descripción | LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS | |
| Fabricantes | ST Microelectronics | |
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TDA9106A
LOW COST DEFLECTION PROCESSOR
FOR MULTISYNC MONITORS
.....HORIZONTAL
SELF-ADAPTATIVE
DUAL PLL CONCEPT
150kHz MAXIMUM FREQUENCY
X-RAY PROTECTION INPUT
I2C CONTROLS : HORIZONTAL POSITION,
FREQUENCY GENERATOR FOR BURN-IN
MODE
....VERTICAL
VERTICAL RAMP GENERATOR
50 TO 165Hz AGC LOOP
GEOMETRY TRACKING WITH V-POS & AMP
I2C CONTROLS :
V-AMP, V-POS, S-CORR, C-CORR
.I2C GEOMETRY CORRECTIONS
VERTICAL PARABOLA GENERATOR
(Pincushion, Keystone, Corner Correction,
Top/bottom Corner Correction Balance)
. HORIZONTAL DYNAMIC PHASE
(Side Pin Balance & Parallelogram)
. HORIZONTAL AND VERTICAL DYNAMIC FO-
CUS (Horizontal Focus Amplitude, Horizontal
Focus Symmetry)
........GENERAL
SYNC PROCESSOR
HOR. & VERT. SYNC OUTPUT FOR MCU
HOR. & VERT. BLANKING OUTPUTS
12V SUPPLY VOLTAGE
8V REFERENCE VOLTAGE
HOR. & VERT. LOCK UNLOCK OUTPUTS
READ/WRITE I2C INTERFACE
HORIZONTAL MOIRE OR DAC OUTPUT
DESCRIPTION
The TDA9106A is a monolithic integrated circuit
assembled in 42 pins shrunk dual in line plastic
package.This IC controlsall the functionsrelated to
the horizontal and vertical deflection in multimodes
or multi-frequency computer display monitors.
The internal sync processor, combinedwith thevery
powerful geometry correction block are making the
TDA9106Asuitablefor very high performancemoni-
tors with very few external components.
It is particularly well suited for high-end 15” and 17”
monitors.
PRELIMINARY DATA
Combined with ST7275 Microcontroller family,
TDA9206 (Video preamplifier) and STV942x
(On-Screen Display controller) the TDA9106A
allows to built fully I2C bus controlled computer
display monitors, thus reducing the number of
external components to a minimum value.
SHRINK42
(Plastic Package)
ORDER CODE : TDA9106A
PIN CONNECTIONS
S/G
MOIRE
PLL1INHIB
PLL2C
HREF
HFLY
HGND
FC2
FC1
C0
R0
PLL1F
HLOCKCAP
HPOS
XRAY
HFOCUSCAP
HFOCUS
VCC
GND
HOUTEM
HOUTCOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 GND
41 SDA
40 SCL
39 5V
38 H/HVIN
37 HLOCKOUT
36 HOUT
35 VSYNCOUT
34 TEST
33 VSYNCIN
32 VFOCUS
31 EWOUT
30 VFLY
29 VOUT
28 VDCOUT
27 VCAP
26 VREF
25 VAGCCAP
24 VGND
23 VBLKOUT
22 HBLKOUT
November 1997
This is advance information on a new product now in development or undergoing evaluatio n. Details are subject to change without notice.
1/30
1 page  
TDA9106A
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VDD
VIN
VESD
Tstg
Tj
Toper
Parameter
Supply Voltage (Pin 18)
Supply Voltage (Pin 39)
Max Voltage on Pin 6
Pins 15, 21, 22, 23
Pin 1
Pin 4
Pins 3, 33,34,37,38,40,41
Pin 16
Pins 8, 9, 10, 11, 12, 13, 14, 25, 27, 30
ESD susceptibility
Human Body Model,100pF Discharge through 1.5kΩ
EIAJ Norm,200pF Discharge through 0Ω
Storage Temperature
Junction Temperature
Operating Temperature
Value
13.5
5.7
1.8
12
3.6
4
5
6
8
2
300
-40, +150
+150
0, +70
Unit
V
V
V
V
V
V
V
V
V
kV
V
oC
oC
oC
THERMAL DATA
Symbol
Parameter
Rth (j-a) Junction-ambient Thermal Resistance
Max.
Value
65
Unit
oC/W
SYNCHRO PROCESSOR
Operating Conditions
Symbol
HsVR
MinD
Mduty
VsVR
VSW
VSmD
VextM
Parameter
Horizontal Sync Input Voltage
Minimum Horizontal Input Pulses Duration
Maximum Horizontal Input Signal Duty Cycle
Vertical Sync Input Voltage
Minimum Vertical Sync Pulse Width
Maximum Vertical Sync Input Duty Cycle
Maximum Vertical Sync Width on TTL
H/Vcomposite or S/G
Test Conditions
Pin 38
Pin 38
Pin 38
Pin 33
Pin 33
Pin 33
Pins 1, 38
Electrical Characteristics (VDD = 5V, Tamb = 25oC)
Symbol
Parameter
VSGDC S/G Clamped DC Level
ISGbias Internal Diode Bias Current
VSGTh Slicing Level (see application design choice)
VINTH H o r iz on t al a n d V ert i cal I npu t V o lta ge
(Pins 33,38)
RIN Horizontal and Vertical Pull-Up Resistor
VOut Output Voltage (Pins 35,36,37)
TfrOut Falling and Rising Output CMOS Buffer
VHlock Horizontal 1st PLL Lock Output Status (Pin 37)
VoutT Extracted Vsync Integration Time (% of TH) on
H/V Composite or S/G
Test Conditions
Pin 1, I1 = -1µA
Pin 1, V1 = 1.6V
Pin 1
Low Level
High Level
Pins 33,38
Low level
High Level
Pins 35,36,37
Cout = 20pF
Locked
Unlocked
Pin 35, C0 = 820pF
Min.
0
0.7
0
5
Min.
2.2
26
Typ.
Typ.
1
10
0.2
200
0
5
100
0
5
35
Max.
5
25
5
15
750
Unit
V
µs
%
V
µs
%
µs
Max.
0.8
Unit
V
µA
V
V
V
kΩ
V
V
ns
V
V
%
5/30
5 Page 
TDA9106A
VERTICAL SECTION (continued)
Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued)
Symbol
Parameter
Test Conditions Min. Typ. Max. Unit
VERTICAL DYNAMIC FOCUS FUNCTION
VDFDC
TDVDFDC
VDFAMP
VDFKEY
DC Output Voltage with V-Pos Typ
DC Output Voltage Thermal Drift
Parabola Amplitude Function of Vamp (tracking
between Vamp and VDF)
with V-Pos Typ
(see Figure 3) (see Note 13)
Parabola Assymetry Function of VPos Control
(tracking between V-Pos and VDF) with Vamp
Max. (see Note 13)
See Figure 3
See Note 12
Subaddress 05
Byte 10000000
Byte 11000000
Byte 11111111
Subaddress 06
Byte x0000000
Byte x1111111
6V
100 ppm/C
0.9 V
1.6 V
2.5 V
0.5
0.5
Notes : 12. Parameter not tested on each unit but measured during our internal qualification procedure including batches coming from corners
of our process and also temperature characterization.
13. S and C corrections are inhibited so the output sawtooth has a linear shape.
Figure 1 : E/W Output
Figure 2 : Dynamic Horizontal Phase Control
Output
B
EWPARA
A
EWDC
Figure 3 : Vertical Dynamic Focus Function
A
VDFDC
VDFAMP
B
B
A
SPBPARA
DHPCDC
Figure 4 : Keystone Effect on E/W Output
(PCC Inhibited)
Keyadj
11/30
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA9106A.PDF ] | |
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