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PDF TDA9102T Data sheet ( Hoja de datos )

Número de pieza TDA9102T
Descripción H/V PROCESSOR FOR TTL V.D.U
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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TDA9102C/T
H/V PROCESSOR FOR TTL V.D.U
HORIZONTAL SECTION
. SYNCHRONIZATION INPUT : TTL COMPAT-
IBLE, NEGATIVE EDGE TRIGGERED
. SYNCHRONIZATION INDEPENDENT FROM
DUTY CYCLE TIME
. OSCILLATOR : FREQUENCY RANGE FROM
15kHz to 100kHz
. HORIZONTAL OUTPUT PULSE SHAPER
AND SHIFTER
. PHASE COMPARATOR BETWEEN SYN-
CHRO AND OSCILLATOR (PLL1)
. PHASE COMPARATOR BETWEEN FLYBACK
AND OSCILLATOR (PLL2)
. INTERNAL VOLTAGE REGULATOR
. DC COMPATIBLE CONTROLS FOR PHASE
AND FREQUENCY
. HORIZONTAL OUTPUT DUTY CYCLE : 41%
VERTICAL SECTION
. SYNCHRONIZATION INPUT : TTL COMPAT-
IBLE, NEGATIVE EDGE TRIGGERED
. SYNCHRONIZATION INDEPENDENT FROM
DUTY CYCLE TIME
. OSCILLATOR : FREQUENCY RANGE FROM
30Hz to 120Hz
. RAMP GENERATOR WITH VARIABLE GAIN
STAGE
. VERTICAL RAMP VOLTAGE REFERENCE
. INTERNAL VOLTAGE REGULATOR
. DC COMPATIBLE CONTROLS FOR FRE-
QUENCY, AMPLITUDE AND LINEARITY
DESCRIPTION
The TDA9102C/T is a monolithic integrated circuit
for horizontal and vertical sync processing in mono-
chrome and color video displays driven by input
TTL compatible signals.
The TDA9102C/T is supplied in a 20 pin dual in line
package with pin 11 connected to ground and used
for heatsinking.
May 1994
DIP20 (0.25)
(Plastic package)
ORDER CODES : TDA9102C/T
PIN CONNECTIONS
Substrate Ground 11
Vertical Frequency Preset 12
C13 13
Vertical TTL Input 14
Vertical Ramp Output 15
Vertical Amplitude Adjust 16
Vertical Linearity Adjust 17
Linearity Output 18
Vertical Reference Voltage 19
VS 20
10 Horizontal Phase Adjust
9 Phase Comparator 2 Output
8 Horizontal Flyback Input
7 Horizontal Output
6 Horizontal Power Ground
5 C5
4 Horizontal TTL Input
3 Phase Comparator 1 Output
2 C2
1 R1
1/7

1 page




TDA9102T pdf
TDA9102C/T
ELECTRICAL CHARACTERISTICS (continued)
(Tamb = 25oC, VS = 12V, refer to the test circuits, unless otherwise specified)
Symbol
Parameter
Test conditions Min. Typ. Max.
VERTICAL SECTION
K17
Frequency
drift
versus
supply
voltage
K17
=
dF . 106
dV . fV
VS = 10.5V to 15.5V
300
Unit
ppm
V
Technical note 1
HORIZONTAL
OSCILLATOR
Technical note 3
K9 = 67.5 degrees/volt represents the slope of the
oscillator charging period of the waveform at
ϕ1 HOR. SYNC.
Pin 2:
K9
=
360
x 0.75
4
degree
V
V3H
V3H VDC
2
C2
1 R2
if
R1 I1
V3L
3
C1 R3
C3
V3L VDC
fH (nom) = 26.8 kHz
R1 = 6.8k
R2 = 56 k
C2 = 1.8 nF
fpull-in
=
fH
(nom)
V3 V1 /
V1 / R1
R2
=
fH (nom)
If
Io
(A)
where: V1 = 3.5V and V3 - V1is the control
voltage range.
The voltage at Pin 3 is limited by two clamping
diodes at the voltage V3H and V3L
When the PLL1 is synchronized and perfectly
tuned, V3 = V1.
Technical note 4
The second PLL can recover the storage of hori-
zontal output stage maintaining a constant duty
cycle till the trailing edge of the output pulse gets
the trailing edge of the flyback pulse. From this
point on, only the leading edge of the output pulse
will be shifted covering a total phase shift of: 0.30T;
overcoming this value, it will produce a notch in the
output pulse (@ fH = 27kHz).
Technical note 5
The voltage reference at Pin 19 can be used to
polarize the DC operating point of the vertical
booster. This voltage corresponds to the double of
the mean value voltage of the vertical sawtooth at
Pin 13.
Technical note 6
V (V)
VH = 6.8V
V = 6V
VL = 5.2V
Remark: The value of C2 influences the horizontal
oscillator free running frequency; it doesn’t effect
the relative pull-in range. If the horizontal fre-
quency is changed by using R1, the pull-in range
changes accordingly with the formula (A).
Technical note 2
The internal pulse "t5", is generated by the current
generator "I5" charging the external capacitor
"C5", according with the formula (B):
t5 =
C5 .
I5
V5
(B),
t5 =
TH
12
is recommended.
VLL = 2V
VH
ts
VL
=
VH VLL
1/fV
ts
=
(VH VL)
(VH VLL)
1
fV
=
K14
fV
t (s)
1/fv
ts
5/7

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