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PDF TDA8790 Data sheet ( Hoja de datos )
| Número de pieza | TDA8790 | |
| Descripción | 8-bit/ 40 Msps 2.7 to 5.5 V universal analog-to-digital converter | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TDA8790 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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INTEGRATED CIRCUITS
DATA SHEET
TDA8790
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
Product specification
Supersedes data of 1995 May 08
File under Integrated Circuits, IC02
1996 Feb 21
1 page  
Philips Semiconductors
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
Product specification
TDA8790
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDDA
VDDD
VDDO
∆VDD
VI
Vclk(p-p)
IO
Tstg
Tamb
Tj
PARAMETER
analog supply voltage
digital supply voltage
output stages supply voltage
supply voltage difference
VDDA − VDDD
VDDA − VDDO
VDDD − VDDO
input voltage
AC input voltage for switching
(peak-to-peak value)
output current
storage temperature
operating ambient temperature
junction temperature
CONDITIONS
note 1
note 1
note 1
referenced to VSSA
referenced to VSSD
MIN.
−0.3
−0.3
−0.3
MAX.
+7.0
+7.0
+7.0
UNIT
V
V
V
−1.0
−1.0
−1.0
−0.3
−
−
−55
−20
−
+4.0
+4.0
+4.0
+7.0
VDDD
10
+150
+75
+150
V
V
V
V
V
mA
°C
°C
°C
Note
1. The supply voltages VDDA, VDDD and VDDO may have any value between −0.3 V and +7.0 V provided that the supply
voltage ∆VDD remains as indicated.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
thermal resistance from junction to ambient in free air
VALUE
120
UNIT
K/W
1996 Feb 21
5
5 Page 
Philips Semiconductors
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
Product specification
TDA8790
handbook, full pagewidth
V DDD
SLEEP
50 %
output
data
output
data
t dLZ
t dZL
HIGH
HIGH
t dHZ
t dZH
90 %
LOW
50 %
LOW 10 %
TDA8790
SLEEP
50 %
3.3 kΩ
20 pF
V DDD
S1
TEST
t dLZ
t dZL
t dHZ
t dZH
S1
VDDD
VDDD
GND
GND
MBE503
fSLEEP = 100 kHz.
Fig.5 Timing diagram and test conditions of 3-state output delay time.
1996 Feb 21
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet TDA8790.PDF ] | |
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