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PDF TDA8762 Data sheet ( Hoja de datos )

Número de pieza TDA8762
Descripción 10-bit high-speed low-power analog-to-digital converter
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! TDA8762 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
TDA8762
10-bit high-speed low-power
analog-to-digital converter
Product specification
Supersedes data of 1995 Feb 15
File under Integrated Circuits, IC02
1996 Mar 28

1 page




TDA8762 pdf
Philips Semiconductors
10-bit high-speed low-power
analog-to-digital converter
Product specification
TDA8762
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCCA
VCCD
VCCO
VCC
VI
Vclk(p-p)
IO
Tstg
Tamb
Tj
PARAMETER
analog supply voltage
digital supply voltage
output stages supply voltage
supply voltage difference
VCCA VCCD
VCCA VCCO
VCCD VCCO
input voltage
AC input voltage for switching
(peak-to-peak value)
output current
storage temperature
operating ambient temperature
junction temperature
CONDITIONS
note 1
note 1
note 1
referenced to AGND
referenced to DGND
MIN.
0.3
0.3
0.3
MAX.
+7.0
+7.0
+7.0
UNIT
V
V
V
1.0
1.0
1.0
0.3
55
0
+1.0
+1.0
+1.0
+7.0
VCCD
10
+150
+70
+150
V
V
V
V
V
mA
°C
°C
°C
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between 0.3 V and +7.0 V provided that the supply
voltage differences VCC are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
thermal resistance from junction to ambient in free air
VALUE
110
UNIT
K/W
1996 Mar 28
5

5 Page





TDA8762 arduino
Philips Semiconductors
10-bit high-speed low-power
analog-to-digital converter
Product specification
TDA8762
Table 1 Output coding and input voltage (typical values; referenced to AGND, VRB = 1.3 V, VRT = 3.8 V)
BINARY OUTPUT BITS
TWO’S COMPLEMENT OUTPUT BITS
STEP VI(p-p) IR
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
U/F <1.52 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 1.52 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
1 . 100000000011000000001
. . .....................
. . .....................
1022 . 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0
1023 3.58 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
O/F >3.58 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
Table 2 Mode selection
TC OE
X1
00
10
D9 TO D0
high impedance
active; two’s complement
active; binary
high impedance
active
active
IR
handbook, full pagewidth
CLK
tCPH
t CPL
sample N
sample N + 1 sample N + 2
1.4 V
Vl
DATA
D0 to D9
t ds
DATA
N-2
DATA
N-1
td
th
DATA
N
DATA
N+1
2.4 V
1.4 V
0.4 V
MGC037
1996 Mar 28
Fig.4 Timing diagram.
11

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