PDF TDA8760 Data sheet ( Hoja de datos )

Número de pieza	TDA8760
Descripción	10-bit high-speed analog-to-digital converter
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET TDA8760 10-bit high-speed analog-to-digital converter Product speciﬁcation Supersedes data of April 1994 File under Integrated Circuits, IC02 1996 Sep 12 1 page Philips Semiconductors 10-bit high-speed analog-to-digital converter PINNING SYMBOL CLK CLK VCCD1 DGND1 n.c. n.c. VCCA1 AGND1 AGND2 VI VI AGND3 VCCA2 VrefL VrefH AGND4 VCCA3 n.c. n.c. DGND2 VCCD2 CS OTC OGND1 VCCO1 IR D9 VCCO2 D8 OGND2 D7 D6 D5 D4 D3 D2 OGND3 n.c. n.c. D1 1996 Sep 12 PIN DESCRIPTION 1 clock input 2 complementary clock input 3 digital supply voltage (+5 V) 4 digital ground 5 not connected 6 not connected 7 analog supply voltage (+5 V) 8 analog ground 9 analog ground 10 analog input voltage 11 complementary analog input voltage 12 analog ground 13 analog supply voltage (+5 V) 14 reference voltage LOW 15 reference voltage HIGH 16 analog ground 17 analog supply voltage (+5 V) 18 not connected 19 not connected 20 digital ground 21 digital supply voltage (+5 V) 22 chip select input (TTL level input; active HIGH) 23 output two’s complement 24 output ground 25 output supply voltage (+5 V) 26 in-range output 27 data output, bit 9 (MSB) 28 output supply voltage (+5 V) 29 data output, bit 8 30 output ground 31 data output, bit 7 32 data output, bit 6 33 data output, bit 5 34 data output, bit 4 35 data output, bit 3 36 data output, bit 2 37 output ground 38 not connected 39 not connected 40 data output, bit 1 5 Product speciﬁcation TDA8760 5 Page Philips Semiconductors 10-bit high-speed analog-to-digital converter Product speciﬁcation TDA8760 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT EFFECTIVE BITS; notes 4 and 5; see Figs 6, 8 and 9 EB effective bits fi = 4.43 MHz TDA8760K/2 (fclk = 20 MHz) fi = 7.5 MHz effective bits fi = 4.43 MHz TDA8760K/4 (fclk = 40 MHz) fi = 10 MHz fi = 15 MHz TWO-TONE Two-tone two-tone intermodulation rejection fclk = 40 MHz; note 8 − − − − − − 8.90 − 8.70 − 8.80 − 8.80 − 8.70 − −65 − bits bits bits bits bits dB BIT ERROR RATE BER bit error rate fclk = 40 MHz; − fi = 4.43 MHz; VI = ±16 LSB at code 512 2 × 10−12 − times/ samples DIFFERENTIAL GAIN; SEE Fig.5 Gdiff differential gain fclk = 20 MHz; fi = 4.43 MHz − fclk = 40 MHz; fi = 4.43 MHz − 0.5 − 1.0 − % % DIFFERENTIAL PHASE Φdiff differential phase fclk = 40 MHz; fi = 4.43 MHz − 0.1 0.2 deg Analog signal processing in single input mode; see Table 2; 50% clock duty factor; VI(p-p) = VrefH − VrefL = 1.4 V LINEARITY ILE DC integral linearity error DLE DC differential linearity error AILE AC integral linearity error BANDWIDTH (fclk = 40 MHZ); note 9 B Analog bandwidth HARMONICS (fclk = 40 MHZ); see Fig.7 f1 fundamental harmonics (full scale) fall harmonics (full scale); all components second harmonics third harmonics THD total harmonic distortion fclk = 4 MHz fclk = 4 MHz note 3 −1 dB −3 dB fi = 4.43 MHz fi = 4.43 MHz fi = 4.43 MHz; note 2 − − − − − − − − − ±1.0 ±2.0 LSB ±0.6 ±1.0 LSB ±1.2 ±2.0 LSB 140 − 220 − MHz MHz − 0 dB −61 − −62 − −59 − dB dB dB 1996 Sep 12 11 11 Page

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