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PDF TDA8424 Data sheet ( Hoja de datos )
| Número de pieza | TDA8424 | |
| Descripción | Hi-Fi stereo audio processor; I2C-bus | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
TDA8424
Hi-Fi stereo audio processor;
I2C-bus
Product specification
File under Integrated Circuits, IC02
September 1992
1 page  
Philips Semiconductors
Hi-Fi stereo audio processor; I2C-bus
Product specification
TDA8424
FUNCTIONAL DESCRIPTION
Mode selector
The mode selector selects between stereo, sound A and
sound B (in the event of bi-lingual transmission) for OUT R
and OUT L.
Volume control and balance
The volume control consists of two stages (left and right).
In each part the gain can be adjusted between +6 dB and
−64 dB in steps of 2 dB. An additional step allows an
attenuation of ≥ 80 dB. Both parts can be controlled
independently over the whole range, which allows the
balance to be varied by controlling the volume of left and
right output channels.
Stereo, spatial stereo and forced mono mode
It is possible to select three modes: stereo, spatial stereo
or forced mono. The spatial stereo mode handles stereo
transmissions and the forced mono can be used in the
event of stereo signals.
positive supply voltage via a pull-up resistor.
When the bus is free both lines are HIGH.
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock on the SCL line is LOW.
The set-up and hold times are specified in the AC
CHARACTERISTICS.
A HIGH-to-LOW transition of the SDA line while SCL is
HIGH is defined as a start condition.
A LOW-to-HIGH transition of the SDA line while SCL is
HIGH is defined as a stop condition.
The bus receiver will be reset by the reception of a start
condition. The bus is considered to be busy after the start
condition.
The bus is considered free again after a stop condition.
Module address
Data transmission to the TDA8424 starts with the module
address MAD.
Bass control
The bass control can be switched from an emphasis of
15 dB to an attenuation of 12 dB for low frequencies in
steps of 3 dB.
Treble control
The treble control stage can be switched
from +12 dB to −12 dB in steps of 3 dB.
Fig.3 TDA8424 module address.
Bias and power supply
The TDA8424 includes a bias and power supply stage,
which generates a voltage of 0.5 VCC with a low output
impedance and injector currents for the logic part.
Power-on reset
The on-chip power-on reset circuit sets the mute bit to
active, which mutes both parts of the treble amplifier. The
muting can be switched by transmission of the mute bit.
I2C-bus receiver and data handling
BUS SPECIFICATION
The TDA8424 is controlled via the 2-wire I2C-bus by a
microcontroller.
The two wires (SDA - serial data, SCL - serial clock) carry
information between the devices connected to the bus.
Both SDA and SCL are bi-directional lines, connected to a
Subaddress
After the module address byte a second byte is used to
select the following functions:
• Volume left, volume right, bass, treble and switch
functions
The subaddress SAD is stored within the TDA8424. Table
1 defines the coding of the second byte after the module
address MAD.
The automatic increment feature of the slave address
enables a quick slave receiver initialization, within one
transmission, by the I2C-bus controller (see Fig.5).
September 1992
5
5 Page 
Philips Semiconductors
Hi-Fi stereo audio processor; I2C-bus
Product specification
TDA8424
AC CHARACTERISTICS
VCC = 12 V; bass/treble in linear position; stereo mode; spatial stereo off; RL > 10 kΩ; CL < 1000 pF; Tamb = 25 °C;
unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
I2C-bus timing (see Fig.7)
SDA, SCL (PINS 11 AND 12)
fSCL
tHIGH
tLOW
tr
tf
tSU;STA
tHD;STA
tSU;STO
tBUF
clock frequency range
clock HIGH period
clock LOW period
SCL rise time
SCL fall time
set-up time for start condition
hold time for start condition
set-up time for stop condition
time bus must be free before
a new transmission can start
tSU;DAT
data set-up time
Inputs
0−
4−
4.7 −
−−
−−
4.7 −
4−
4.7 −
4.7 −
250 −
100 kHz
− µs
− µs
1 µs
0.3 µs
− µs
− µs
− µs
− µs
− ns
IN L (PIN 1) IN R (PIN 3)
Vi(RMS)
input signal handling
(RMS value)
Ri input resistance
f frequency response (0.5 dB)
at Vu = −12 dB;
THD ≤ 0.5%
2−−V
20 30 40 kΩ
20 −
20 000 Hz
Outputs
OUT R (PIN 9) OUT L (PIN 13)
Vo(RMS)
output voltage range
(RMS value)
RL
ZO
(S+N)/N
load resistance
output impedance
signal plus noise-to-noise ratio
THD
gain = 6 dB
gain = 0 dB
gain ≤ −20 dB
total harmonic distortion
gain = +6 dB to −40 dB
gain = 0 dB to −40 dB
gain = −12 dB to −40 dB
at Vi(max) ≤ 2 V;
THD ≤ 0.7%
weighted in accordance
with CCIR 468-2;
Vo = 600 mV
f = 20 Hz to 12.5 kHz
Vi(RMS) = 0.3 V
Vi(RMS) = 0.6 V
Vi(RMS) = 2.0 V
0.6
10
−
−
−
−
−
−
−
−−V
− − kΩ
− 100 Ω
78 −
86 −
68 −
0.05 −
0.07 0.4
0.1 −
dB
dB
dB
%
%
%
September 1992
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet TDA8424.PDF ] | |
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