|
|
PDF TDA8303 Data sheet ( Hoja de datos )
| Número de pieza | TDA8303 | |
| Descripción | Small signal combination IC for black/white TV | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de TDA8303 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
|
No Preview Available !
INTEGRATED CIRCUITS
DATA SHEET
TDA8303
TDA8303A
Small signal combination IC for
black/white TV
Preliminary specification
File under Integrated Circuits, IC02
July 1992
1 page  
Philips Semiconductors
Small signal combination IC for black/white
TV
Preliminary specification
TDA8303
TDA8303A
PINNING
PIN DESCRIPTION
1 AGC take-over
2 vertical ramp generator
3 vertical drive
4 vertical feedback
5 tuner AGC
6 ground
7 supply voltage input
8 video IF input
9 video IF input
10 IF AGC
11 volume control/start horizontal oscillator
12 audio output
13 sound demodulator
14 sound IF decoupling
15 sound IF input
16 ground (for some critical parts)
17 video amplifier output
18 AFC output
19 AFC S/H, AFC switch
20 video demodulator tuned circuit
21 video demodulator tuned circuit
22 coincidence detector
23 horizontal oscillator
24 phase 1 detector
25 sync separator input
26 horizontal drive output
27 horizontal flyback input
28 phase 2 detector
Sound circuit
The sound quality of the TDA8303/TDA8303A compared
with the predecessors has been improved at weak signal
conditions. The improvement has been achieved by the
new IF amplifier which is less sensitive for radiation from
the sound IF amplifier and by change of the ground and
supply connections in the IC. When out-of-sync condition
is detected by the coincidence detector the sound output
is muted. When no mute is required the minimum voltage
level on pin 22 should be clamped to a high level of 5 V.
At this level the gating of the AGC is switched off and the
phase 1 detector has a high output current for reliable
catching of a new transmitter.
Vertical synchronization
The TDA8303/TDA8303A embodies a synchronized
divider system for generating the vertical sawtooth at pin 2
having several advantages and features such as:
• The vertical frequency is alignment free. The divider
automatically adapts to a vertical frequency of 50 Hz or
60 Hz including automatic amplitude correction and its
operating modes offer maximum
interference/disturbance protection.
• A discriminator-window checks the accuracy of the
vertical trigger pulse. Internally clock pulses are
generated by doubling the line frequency. The divider
operates in the 60 Hz mode when the trigger pulse
appears before count 576, otherwise the 50 Hz mode
will be active.
• The divider system operates with two different reset
windows for maximum interference/disturbance
protection. The windows are activated via an up/down
counter. The counter increases its counter-value by 1 for
each time the separated vertical sync pulse appears
within the selected window, otherwise the counter value
is decreased by 1.
AGC circuit
The AGC circuit of the TDA8303/TDA8303A is a top-sync
detector. The video signal coming from the video amplifier
passes a 2nd order low-pass filter before it is compared
with an internal reference level. The comparator stage is
gated when the horizontal oscillator is synchronized with
the video signal, such that interference pulses outside the
gating time have no influence on the gain control.
Modes of operation
Large search window: divider ratio between 488 and 576.
This mode is valid for the following conditions:
• Divider is looking for a new transmitter
• Divider ratio found does not comply with the narrow
window specification limits
• Up/down counter value of the divider system, operating
in the narrow window mode, drops below count 10
July 1992
5
5 Page 
Philips Semiconductors
Small signal combination IC for black/white TV
Preliminary specification
TDA8303
TDA8303A
SYMBOL
PARAMETER
CONDITIONS MIN. TYP. MAX. UNIT
Vertical circuit (note 24)
VERTICAL RAMP GENERATOR
I2
I2
V2(p−p)
t
input current during scan
discharge current during retrace
sawtooth amplitude (peak-to-peak value)
interlace timing of the internal pulses
− − 2 µA
−
0.8 −
mA
−
1.9 −
V
30 32 34 µs
VERTICAL OUTPUT
I3 available output current
V3 maximum available output voltage
V3 = 4 V
− − 3 mA
I3 = 0.1 mA 4.4 5 − V
VERTICAL FEEDBACK INPUT
V4 DC input voltage
2.9 3.3 3.7 V
V4(p−p)
AC input voltage (peak-to-peak value)
− 1−V
I4 input current
− − 12 µA
∆tp internal pre-correction to sawtooth
− 3−%
deviation amplitude
50/60 Hz
− −4%
temperature dependency of the amplitude
Tamb = 20 to
65 °C
−
−2%
Notes to the characteristics
1. Pin 11 has a double function. When during switch-on a current of 9 mA is supplied to this pin, it is used to start the
horizontal oscillator. The main supply can then be obtained from the horizontal deflection stage. When no current is
supplied to this pin it can be used as a volume control.
2. On set AGC.
3. The input impedance has been chosen such that a SAW filter can be employed.
4. Measured with 0 dB = 450 µV.
5. Measured at 10 mV RMS top sync input signal.
6. Projected zero point; i.e. with switched demodulator.
7. White 10% of the top sync amplitude.
8. Measured according to the test line illustrated by Fig.2. The differential gain is expressed as a percentage of the
difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking
level. The differential phase is defined as the difference in degrees between the largest and smallest phase angle.
The differential gain and phase are measured with a DSB signal.
9. This figure is valid for the complete video signal amplitude (peak white-to-black); see Fig.3. The non−linearity is
expressed as a percentage of the maximum deviation of a luminance step from the mean step, with respect to the
mean step.
10. The test set−up and input conditions are illustrated by Fig.4. The figures are measured at an input signal of 10 mV
RMS.
11. Measured with a source impedance of 75Ω.
The signal-to-noise ratio = 20 log -V----n--V-(--R-O---M---b-S--l-)-a---c-a--k-t----B-t--o---=---w---5-h----iM-t--e--H-----z-
12. The sound circuit is measured (unless otherwise specified) with an input signal of V15 of 50 mV RMS, a carrier
frequency of 5.5 MHz at a ∆f of 27.5 kHz. The QL of the demodulator tuned circuit is 16 and the volume control is
July 1992
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet TDA8303.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TDA8302 | SMALL SIGNAL COMBINATION IC | NXP Semiconductors |
| TDA8303 | Small signal combination IC for black/white TV | NXP Semiconductors |
| TDA8303A | Small signal combination IC for black/white TV | NXP Semiconductors |
| TDA8304 | SMALL SIGNAL COMBINATION IC FOR COLOUR TV | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |