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PDF TDA7562 Data sheet ( Hoja de datos )
| Número de pieza | TDA7562 | |
| Descripción | MULTIFUNCTION QUAD POWER AMPLIFIER WITH BUILT-IN DIAGNOSTICS FEATURES | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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TDA7562
MULTIFUNCTION QUAD POWER AMPLIFIER
WITH BUILT-IN DIAGNOSTICS FEATURES
s DMOS POWER OUTPUT
s HIGH OUTPUT POWER CAPABILITY 4x25W/
4Ω @ 14.4V, 1KHZ, 10% THD, 4x35W EIAJ
s MAX. OUTPUT POWER 4x60W/2Ω
s FULL I2C BUS DRIVING:
– ST-BY
– INDEPENDENT FRONT/REAR SOFT PLAY/
MUTE
– SELECTABLE GAIN 30dB - 16dB (FOR
LOW NOISE LINE OUTPUT FUNCTION)
– I2C BUS DIGITAL DIAGNOSTICS
s FULL FAULT PROTECTION
s DC OFFSET DETECTION
s FOUR INDEPENDENT SHORT CIRCUIT
PROTECTION
s CLIPPING DETECTOR PIN WITH
SELECTABLE THRESHOLD (2%/10%)
s ST-BY/MUTE PIN
s ESD PROTECTION
DESCRIPTION
The TDA7562 is a new BCD technology Quad
MULTIPOWER BCD TECHNOLOGY
MOSFET OUTPUT POWER STAGE
FLEXIWATT27 (Vertical)
Bridge type of car radio amplifier in Flexiwatt27V
package specially intended for car radio applica-
tions. Thanks to the DMOS output stage the
TDA7562 has a very low distortion allowing a clear
powerful sound. This device is equipped with a full
diagnostics array that communicates the status of
each speaker through the I2C bus.The possibility
to control the configuration and the behaviour of
the device by means of the I2C bus makes
TDA7562 a very flexible machine.
BLOCK DIAGRAM
ST-BY/MUTE
IN RF
F
IN RR
R
IN LF
F
IN LR
R
SVR
CLK DATA VCC1 VCC2
I2CBUS
Mute1 Mute2
Thermal
Protection
& Dump
Reference
Clip
Detector
16/30dB
16/30dB
16/30dB
16/30dB
Short Circuit
Protection &
Diagnostic
Short Circuit
Protection &
Diagnostic
Short Circuit
Protection &
Diagnostic
Short Circuit
Protection &
Diagnostic
CD_OUT
OUT RF+
OUT RF-
OUT RR+
OUT RR-
OUT LF+
OUT LF-
OUT LR+
OUT LR-
AC_GND
RF RR
LF LR
PW_GND
TAB
S_GND
May 2003
1/17
1 page  
TDA7562
ELECTRICAL CHARACTERISTICS (continued)
(Refer to the test circuit, VS = 14.4V; RL = 4Ω; f = 1KHz; Tamb = 25°C; unless otherwise specified.)
Symbol
Parameter
Test Condition
Min. Typ. Max.
DIAGNOSTICS (Power Amplifier Mode or Line Driver Mode)
Pgnd
Short to GND det. (below this
limit, the Output is considered in
Short Circuit to GND)
Power Amplifier in Mute or Play,
one or more short circuits
protection activated
1.2
Pvs Short to VS det. (above this limit,
the Output is considered in Short
Circuit to VS)
Vs -1.2
Pnop
Normal operation thresholds.
(Within these limits, the Output is
considered without faults).
1.8 Vs -1.8
Lsc Shorted Load det.
Power Amplifier Mode
0.5
Line Driver Mode
1.5
VO Offset Detection
±1.5 ±2 ±2.5
I2C BUS INTERFACE
fSCL Clock Frequency
400
VIL Input Low Voltage
1.5
VIH Input High Voltage
2.3
Unit
V
V
V
Ω
Ω
V
KHz
V
V
5/17
5 Page 
TDA7562
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7562 and viceversa takes place through the 2 wires I2C BUS inter-
face, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).
Data Validity
As shown by fig. 16, the data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Start and Stop Conditions
As shown by fig. 17 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
Acknowledge
The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 18).
The receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so
that the SDAline is stable LOW during this clock pulse.
* Transmitter
– master (µP) when it writes an address to the TDA7562
– slave (TDA7562) when the µP reads a data byte from TDA7562
** Receiver
– slave (TDA7562) when the µP writes an address to the TDA7562
– master (µP) when it reads a data byte from TDA7562
Figure 16. Data Validity on the I2CBUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
Figure 17. Timing Diagram on the I2CBUS
CHANGE
DATA
ALLOWED
SCL
SDA
START
Figure 18. Acknowledge on the I2CBUS
SCL 1 2
D99AU1032
3
7
D99AU1031
I2CBUS
STOP
89
SDA
START
MSB
D99AU1033
ACKNOWLEDGMENT
FROM RECEIVER
11/17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet TDA7562.PDF ] | |
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