PDF TDA7522 Data sheet ( Hoja de datos )

Número de pieza	TDA7522
Descripción	Digital Servo & Decoder
Fabricantes	ST Microelectronics
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TDA7522 Digital Servo & Decoder PRODUCT PREVIEW s BUILT IN 8Bit MICROCONTROLLER (STANDARD ST7) with: – 24 KByte ROM available for ST7 & Servo-Audio DSP – 1024Byte RAM, including 128byte stack – 4KByte RAM for CD-Text memory (for 1block) – Built in R-W subcode buffer (Max. 144Byte 8packs) for CD-Text – 24 bit general I/O port (PoartA[7-0], PortB[7-0], PortC[7-0]) – One External Interrupt (16 IRQ encoder inside) – 16bit free running counter timer – 8bit 1ch general purpose A/D – I2C bus I/F TQFP80 (14 x 14 x 1.40mm body) – Watch dog – Kenwood I/F s STAND-BY MODE (Stop all clocks and Shut down power of Peripheral (PON pin)) s BUILT IN SERVO & AUDIO DIGITAL SIGNAL PROCESSOr (SAC-DSP) inclusive of: – 1024x19bit Program RAM – 512x16bit Coefficient RAM – 1024x20bit Data RAM – 128x6bit Decimation RAM – MAC: 16 bit (Coefficients) x 20 bit (data) multiplier with 38 bit adder – Instruction execution rate as high as 56MIPS s BUILT IN PROGRAMMABLE CLOCK GENERATOR PLL s PERIPHERALS for CD PLAYER APPLICATION – Data Acquisition, Erasure correction, CLV&CAV controller – Subcode decoder (CD-Text, CD-Graphic I/F) – Shock proof memory controller, Disturbance detector – Decimation filter s ACTUATORS DRIVING MODE SELECTABLE between PWM or PDM MODE s 256Fs / 384Fs (16.9344MHz) CLOCK INPUT. May 1998 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/23 1 page TDA7522 Pin Number 33 34 35 36 Name TESTEN SCK SDA SCANEN 37 KASEL 38 KTEST 39 KSEARCH 40 MSTOP 41 SLEDL 42 K_VER_HOR 43 WFCK 44 EXCK 45 SBSO 46 SCOR 47 DOUT 48 CS 49 SRQ 50 CORE_VDD_3 51 CORE_VSS_3 52 DATAS 53 DATAM 54 CLK 55 DRS 56 DWR 57 CAS 58 RAS 59 DRA11 60 DRA10 61 DRA9 62 DRA8 63 DRA7 64 DRA6 Function I I I/O I I/O I/O I/O I/O I/O I/O O I O O O I/O I/O Vdd Gnd I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description Test enable signal (Active low) IIC I/F clock signal IIC I/F data Scan enable (active high) or select DRAM outputs as TEST outputs when TESTEN is inactive DAC polarity selection pin or ST7 GPIO PA0 User test mode selection or ST7 GPIO PA1 Gain change during search or ST7 GPIO PA3 interrupt request/stand-by pin or ST7 GPIO PC5 SLED limit switch or ST7 GPIO PC6 Indication of vertical or horizontal operation or ST7 GPIO PA4 Write Frame clock for Subcode P-W output SBSO readout clock input Subcode P-W serial output Subcode sync output SPDIF Digital audio output ST7 GPIO PC4 ST7 GPIO PC3 Digital Power supply Digital Ground ST7 GPIO PC2 ST7 GPIO PC1 ST7 GPIO PC0 Shock proof memory Read control Shock proof memory Write control Shock proof memory Column address select Shock proof memory Row address select DRAM Address 11 DRAM Address 10 DRAM Address 9 or Mirror signal output DRAM Address 8 or TZC (Tracking Zero Cross) signal output DRAM Address 7 or FOK (Focus OK) signal output DRAM Address 6 or ST7 GPIO PB7 or PLLINF signal output 5/23 5 Page Address Block Register name 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h PWM /PDM SLED_CR: Sled Control Register SLED_DR: Data to control the sled by ST7 SPDL_DR: Data to control spindle motor PWM_CR: Pwm output control register, PLL PLL_CR1: Control Register 1 CLKCNTL: Clock Control Register CLV/CAV CLV_CR1: Control Register 1 CLV_CR2: Control Register 2 CLV_CR3: Control Register 3 Decimation DEC_SR: Decimation Status Register DEC_CR: Decimation Control Register KIF KENWOOD I/F: Register 1 Interface KENWOOD I/F: Register 2 Interrupt MASK1: Interrupt Mask Enable Register MASK MASK2: Interrupt Mask Enable Register CIRC CONFIG1: Configuration register for CIRC CONFIG2: Configuration register for CIRC FIFO1: Offset between read & write pointer FIFO2: Status register for FIFO C1ERRS: Error number by C1 decoder C2ERRS: Error number by C2 decoder DAC DAC_CSR: Control /Status Register SAC_DSP DATA_LB: Lower Byte Data Register DATA_MB: Middle Byte Data Register DATA_UP: Upper Nibble Data + service bit DATA_AR_LB: Data Address COEF_AR_LB: Coefficient Address PROG_AR_LB: Program Address DCPSR: Miscellaneous Control/Data Reg. DSP_ALU1: ALU contains, LSBs DSP_ALU2: ALU contains, MSBs AUDIOC: Audio Control Register DSP_CR: Control Register SHOCK_CMP: Shock Comparor CXD G1-EQUALISER: Coefficient Value (Crossover G2-EQUALISER: Coefficient Value Detection) G3-EQUALISER: Coefficient Value TEST MUX_1: used only on development version SELECTION MUX_2: used only on development version TDA7522 Reset Status Remarks 00h R/W Register 00h R/W Register 00h R/W Register 00h R/W Register Not Available 40h R/W Register 00h R/W Register 05h R/W Register 00h R/W Register 40h R/W Register 00h R Register 00h R/W Register Not Available 00h R/W Register 00h R/W Register 00h R /W Register 00h R/W Register 1Ah R/W Register 19h R/W Register C0h R Register 00h R/W Register 00h R/W Register 00h R/W Register 00h R/W Register 00h R/W Register 00h R/W Register 00h R/W Register 00h R/W Register 00h R/W Register 00h R/W Register 00h R/W Register 00h R Register 00h R Register 00h R/W Register 00h R/W Register 00h R/W Register Not Available Not Available Not Available Not Available 00h R/W Register 00h R/W Register 00h R/W Register R/W Register R/W Register 11/23 11 Page

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