|
|
PDF TDA7401D Data sheet ( Hoja de datos )
| Número de pieza | TDA7401D | |
| Descripción | DIGITALLY CONTROLLED AUDIO PROCESSOR WITH LOUDSPEAKERS EQUALIZER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de TDA7401D (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
|
No Preview Available !
® TDA7401
DIGITALLY CONTROLLED AUDIO PROCESSOR
WITH LOUDSPEAKERS EQUALIZER
FOUR HIGH PASS CHANNELS
ONE STEREO LOW PASS CHANNEL WITH
GAIN CONTROL
DIRECT MUTE PIN
FULLY PROGRAMMABLE VIA I2C BUS
DESCRIPTION
The TDA7401 is an upgrade of the TDA7435
audioprocessor.
Due to a highly linear signal processing, using
CMOS-switching techniques very low distortion
and very low noise are obtained.
Second order high pass and low pass filters with
programmable corner frequencies provide the
loudspeaker equalization.
SO28
ORDERING NUMBER: TDA7401D
Very low DC stepping is obtained by using a
BICMOS technology.
BLOCK DIAGRAM
HP FL 1
HP FL 2
HP FR 1
HP FR 2
HP RL 1
HP RL 2
HP RR 1
HP RR 2
22
21
20
19
18
17
16
15
HP FILTER
HP FILTER
HP FILTER
HP FILTER
AUX 1 IN L
AUX 1 IN R
1
2
GAIN
+20/-79dB
MUTE
3
MUTE
SDA SCL DGND AGND CREF VCC
27 26 25 24 23 28
I2C BUS
SUPPLY
12
OUT REF
MUX
10
HP FL OUT
11
HP FR OUT
13
HP RL OUT
14
HP RR OUT
9
AUX 2 OUT L
8
AUX 2 OUT R
45
CR1 CL1
76
CR2 CL2
D98AU822A
January 1999
1/10
1 page  
TDA7401
I2C BUS INTERFACE
Data transmission from microprocessor to the
TDA7401 and viceversa takes place thru the 2
wires I2C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data Validity
As shown in fig. 2, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.3 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
A STOP conditions must be sent before each
START condition.
Byte Format
Every byte transferred to the SDA line must con-
Figure 3. Data Validity on the I2CBUS
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 4). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse time.
In this case the master transmitter can generate
the STOP information in order to abort the transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the µP can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 4. Timing Diagram of I2CBUS
Figure 5. Acknowledge on the I2CBUS
5/10
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet TDA7401D.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TDA7401 | DIGITALLY CONTROLLED AUDIO PROCESSOR WITH LOUDSPEAKERS EQUALIZER | ST Microelectronics |
| TDA7401D | DIGITALLY CONTROLLED AUDIO PROCESSOR WITH LOUDSPEAKERS EQUALIZER | ST Microelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |