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PDF UTI760A Data sheet ( Hoja de datos )
| Número de pieza | UTI760A | |
| Descripción | UTI760A RTS Remote Terminal for Stores | |
| Fabricantes | ETC | |
| Logotipo |  |
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UTI760A RTS Remote Terminal for Stores
FEATURES
Ë Complete MIL-STD-1760A Notice I through III
remote terminal interface
Ë 1K x 16 of on-chip static RAM for message data,
completely accessible to host
Ë Self-test capability, including continuous loop-back
compare
Ë Programmable memory mapping via pointers for
efficient use of internal memory, including buffering
multiple messages per subaddress
Ë RT-RT Terminal Address Compare
Ë Command word stored with incoming data for
enhanced data management
Ë User selectable RAM Busy (RBUSY) signal for slow
or fast processor interfacing
Ë Full military operating temperature range, -55°C to
+125°C, screened to the specific test methods listed in
Table I of MIL-STD-883, Method 5004, Class B, also
Standard Military Drawing available
Ë Available in 68-pin pingrid array package
INTRODUCTION
The UT1760A RTS is a monolithic CMOS VLSI solution
to the requirements of the dual-redundant MIL-STD-1553B
interface as specified by MIL-STD-1760A. Designed to
reduce cost and space in the mission stores interface, the
RTS integrates the remote terminal logic with a user-
configured 1K x 16 static RAM. In addition, the RTS has a
flexible subsystem interface to permit use with most
processors or controllers.
The RTS provides all protocol, data handling, error
checking, and memory control functions, as well as
comprehensive self-test capabilities. The RTS’s memory
meets all of a mission store’s message storage needs through
user-defined memory mapping. This memory-mapped
architecture allows multiple message buffering at
OUT
IN
OUT
IN
DECODER
MCSA(4:0)
MODE CODE/
SUBADDRESS
RTA(4:0)
CONTROL
REMOTE TERMINAL INPUTS
ADDRESS
COMMAND
RECOGNITION
CONTROL AND
ERROR LOGIC
STATUS
OUTPUTS
DECODER
ENCODER
MUX
1K X 16 RAM
ADDR(9:0)
PTR REGISTER
DATA(15:0)
CLOCK AND RESET 12MHz
LOGIC
RESET
2MHz
Figure 1. UT1760A RTS Functional Block Diagram
RTS-1
1 page  
Subaddress/Mode Code
Transmit Vector Word Mode Code
Receive Subaddress
01
Receive Subaddress
02
Receive Subaddress
03
Receive Subaddress
04
Receive Subaddress
05
Receive Subaddress
06
Receive Subaddress
07
Receive Subaddress
08
Receive Subaddress
09
Receive Subaddress
10
Receive Subaddress
11
Receive Subaddress
12
Receive Subaddress
13
Receive Subaddress
14
Receive Subaddress
15
Receive Subaddress
16
Receive Subaddress
17
Receive Subaddress
18
Receive Subaddress
19
Receive Subaddress
20
Receive Subaddress
21
Receive Subaddress
22
Receive Subaddress
23
Receive Subaddress
24
Receive Subaddress
25
Receive Subaddress
26
Receive Subaddress
27
Receive Subaddress
28
Receive Subaddress
29
Receive Subaddress
30
Synchronize w/Data Word Mode Code
RAM Location
3C0 (hex)
3C1 (hex)
3C2 (hex)
3C3 (hex)
3C4 (hex)
3C5 (hex)
3C6 (hex)
3C7 (hex)
3C8 (hex)
3C9 (hex)
3CA (hex)
3CB (hex)
3CC (hex)
3CD (hex)
3CE (hex)
3CF (hex)
3D0 (hex)
3D1 (hex)
3D2 (hex)
3D3 (hex)
3D4 (hex)
3D5 (hex)
3D6 (hex)
3D7 (hex)
3D8 (hex)
3D9 (hex)
3DA (hex)
3DB (hex)
3DC (hex)
3DD (hex)
3DE (hex)
3DF (hex)
Subaddress/Mode Code
RAM Location
Transmit Last Command Mode Code
Transmit Subaddress
01
Transmit Subaddress
02
Transmit Subaddress
03
Transmit Subaddress
04
Transmit Subaddress 05
Transmit Subaddress 06
Transmit Subaddress 07
Transmit Subaddress 08
Transmit Subaddress 09
Transmit Subaddress 10
Transmit Subaddress 11
Transmit Subaddress 12
Transmit Subaddress 13
Transmit Subaddress 14
Transmit Subaddress 15
Transmit Subaddress 16
Transmit Subaddress 17
Transmit Subaddress 18
Transmit Subaddress 19
Transmit Subaddress 20
Transmit Subaddress 21
Transmit Subaddress 22
Transmit Subaddress 23
Transmit Subaddress 24
Transmit Subaddress 25
Transmit Subaddress 26
Transmit Subaddress 27
Transmit Subaddress 28
Transmit Subaddress 29
Transmit Subaddress 30
Transmit Bit Word Mode Code
3E0 (hex)
3E1 (hex)
3E2 (hex)
3E3 (hex)
3E4 (hex)
3E5 (hex)
3E6 (hex)
3E7 (hex)
3E8 (hex)
3E9 (hex)
3EA (hex)
3EB (hex)
3EC (hex)
3ED (hex)
3EE (hex)
3EF (hex)
3F0 (hex)
3F1 (hex)
3F2 (hex)
3F3 (hex)
3F4 (hex)
3F5 (hex)
3F6 (hex)
3F7 (hex)
3F8 (hex)
3F9 (hex)
3FA (hex)
3FB (hex)
3FC (hex)
3FD (hex)
3FE (hex)
3FF (hex)
1.3 Internal Registers
The RTS uses two internal registers to allow the host to
control the RTS operation and monitor its status. The host
uses the Control (CTRL) signal along with Chip Select (CS),
Read/Write (RD/WR), and Output Enable (OE) to read the
16-bit Status Register or write to the 13-bit Control Register.
No address data is needed to select a register. The Control
Register toggles bits in the MIL-STD-1553B status word,
enables the biphase inputs, recognizes broadcast
commands, selects Notice I and II or III, determines RAM
Busy (RBUSY) timing, selects disconnect or terminal active
flag, and puts the part in self-test mode. The Status Register
supplies operational status of the UT1760A RTS to the host.
These registers must be initialized before attempting RTS
operation. Internal registers can be accessed while RBUSY
is active.
RTS-5
5 Page 
Table 3. Subaddress and Mode Code Definitions Per MIL-STD-1760A Notice III
Subaddress Field
Binary (Decimal)
00000 (00)
00001 (01)
00010 (02)
00011 (03)
00100 (04)
00101 (05)
00110 (06)
00111 (07)
01000 (08)
01001 (09)
01010 (10)
01011 (11)
01100 (12)
01101 (13)
01110 (14)
01111 (15)
10000 (16)
10001 (17)
10010 (18)
10011 (19)
10100 (20)
10101 (21)
10110 (22)
10111 (23)
11000 (24)
11001 (25)
11010 (26)
11011 (27)
11100 (28)
11101 (29)
11110 (30)
11111 (31)
Message Format
Receive
Transmit
B.40.1.1.3 1
B.40.1.1.3
Reserved B.40.2.1 2 Store Description
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
Reserved
Reserved
User Defined
User Defined
User Defined
B.40.2.2.1 3
User Defined
B.40.2.2.1
User Defined
User Defined
User Defined
B.40.1.1.5.8 4
User Defined
B.40.1.5.8
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
B.40.2.2.4 5
User Defined
B.40.2.2.5 6
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
B.40.2.2.4
B.40.2.2.5
User Defined
User Defined
User Defined
User Defined
User Defined
User Defined
B.40.1.1.3
B.40.1.1.3
Description
Mode Code Indicator
Test Only
Mission Store Control/Monitor
Mass Data Transfer
Nuclear Weapon
Nuclear Weapon
Mode Code Indicator
Notes:
1. Refer to section B.40.1.1.3 of the MIL-STD-1760A specification for definition.
2. Refer to section B.40.2.1 of the MIL-STD-1760A specification for definition.
3. Refer to section B.40.2.2.1 of the MIL-STD-1760A specification for definition.
4. Refer to section B.40.1.1.5.8 of the MIL-STD-1760A specification for definition.
5. Refer to section B.40.2.2.4 of the MIL-STD-1760A specification for definition.
6. Refer to section B.40.2.2.5 of the MIL-STD-1760A specification for definition.
7. Reserved subaddresses illegalized; Message Error bit and pin set; SW transmitted.
RTS-11
11 Page | ||
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| PDF Descargar | [ Datasheet UTI760A.PDF ] | |
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