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PDF USBN9604 Data sheet ( Hoja de datos )
| Número de pieza | USBN9604 | |
| Descripción | USBN9603/USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de USBN9604 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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- May 1998
June 2003
Revision 1.3
USBN9603/USBN9604 Universal Serial Bus
Full Speed Node Controller with Enhanced DMA Support
General Description
The USBN9603/4 are integrated, USB Node controllers.
Other than the reset mechanism for the clock generation cir-
cuit, these two devices are identical. All references to “the
device” in this document refer to both devices, unless other-
wise noted.
The device provides enhanced DMA support with many au-
tomatic data handling features. It is compatible with USB
specification versions 1.0 and 1.1, and is an advanced ver-
sion of the USBN9602.
The device integrates the required USB transceiver with a
3.3V regulator, a Serial Interface Engine (SIE), USB end-
point (EP) FIFOs, a versatile 8-bit parallel interface, a clock
generator and a MICROWIRE/PLUS™ interface. Seven
endpoint pipes are supported: one for the mandatory con-
trol endpoint and six to support interrupt, bulk and isochro-
nous endpoints. Each endpoint pipe has a dedicated FIFO,
8 bytes for the control endpoint and 64 bytes for the other
endpoints. The 8-bit parallel interface supports multiplexed
and non-multiplexed style CPU address/data buses. A pro-
grammable interrupt output scheme allows device configu-
ration for different interrupt signaling requirements.
Outstanding Features
q Low EMI, low standby current, 24 MHz oscillator
q Advanced DMA mechanism
q Fully static HALT mode with asynchronous wake-up
for bus powered operation
q 5V or 3.3V operation
q Improved input range 3.3V signal voltage regulator
q All unidirectional FIFOs are 64 bytes
q Power-up reset and startup delay counter simplify sys-
tem design
q Simple programming model controlled by external controller
q Available in two packages
— USBN9603/4SLB: small footprint for new designs
and portable applications
— USBN9603/4-28M: standard package, pin-to-pin
compatible with USBN9602-28M
Block Diagram
CS RD WR A0/ALE D7-0/AD7-0 INTR MODE1-0
Microcontroller Interface
RESET
VCC
GND
Endpoint/Control FIFOs
Serial Interface Engine (SIE)
Media Access Controller (MAC)
Physical Layer Interface (PHY)
24 MHz
Oscillator
Clock
Generator
Clock
Recovery
USB Event
Detect
Transceiver
VReg
D+ D- Upstream Port
XIN
XOUT
CLKOUT
V3.3
AGND
National Semiconductor is a registered trademark of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders.
© National Semiconductor Corporation, 2003
www.national.com
1 page  
Table of Contents (Continued)
7.3 REGISTER MAP ........................................................................................................................ 50
8.0 Device Characteristics
8.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................ 52
8.2 DC ELECTRICAL CHARACTERISTICS ................................................................................... 52
8.3 AC ELECTRICAL CHARACTERISTICS .................................................................................... 53
8.4 PARALLEL INTERFACE TIMING (MODE1-0 = 00B) ................................................................ 54
8.5 PARALLEL INTERFACE TIMING (MODE1-0 = 01B) ................................................................ 55
8.6 DMA SUPPORT TIMING ........................................................................................................... 57
8.7 MICROWIRE INTERFACE TIMING (MODE1-0 = 10B) ............................................................. 58
8.8 RESET TIMING) ........................................................................................................................ 58
5 www.national.com
5 Page 
2.0 Functional Overview (Continued)
D7-0/AD7-0/SO
A0/ALE/SI
CS RD WR/SK
DACK DRQ
Microcontroller Interface
(Parallel and Serial)
INTR MODE1-0
RESET
VCC
GND
Endpoint/Control FIFOs
Control
Status
RX
TX
24 MHz
Oscillator
PLL
x2
XIN
XOUT
Clock
Generator
CLKOUT
SIE
Media Access Controller (MAC)
Physical Layer Interface (PHY)
Clock
Recovery
USB Event
Detect
Transceiver
VReg
V3.3
AGND
D+ D-
Upstream Port
Figure 2. USBN9603/4 Block Diagram
11 www.national.com
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet USBN9604.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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