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PDF USBN9602 Data sheet ( Hoja de datos )
| Número de pieza | USBN9602 | |
| Descripción | USBN9602 (Universal Serial Bus) Full Speed Function Controller With DMA Support | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de USBN9602 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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November 1998
USBN9602 (Universal Serial Bus)
Full Speed Function Controller With DMA Support
1.0 General Description
The USBN9602 is an integrated USB Node controller com- trol endpoint EP0 and six FIFOs for an additional six unidi-
patible with the USB Specification Versions 1.0 and 1.1. rectional Endpoint Pipes to support USB interrupt, bulk and
Integrated onto a single IC are the required USB trans- isochronous data transfers. The 8-bit parallel interface sup-
ceiver with a 3.3V Regulator, Media Access Controller, ports multiplexed and non-multiplexed style CPU
USB endpoint (EP) FIFOs, a versatile 8-bit parallel inter- address/data buses. A programmable interrupt output
face, MICROWIRE/PLUS™ Interface and a clock genera- scheme allows device configuration for different interrupt
tor. A total of seven FIFO buffers support the different USB signaling requirements.
messages: one bidirectional FIFO for the mandatory con-
Block Diagram
CS
RD WR
A0/ALE D[7:0]/AD[7:0] INTR MODE[1:0]
Microcontroller Interface
RESET
Vcc
GND
Endpoint/Control FIFOs
Control
Status
48 MHz
Oscillator
XIN
XOUT
RX
TX
SIE
Media Access Controller (MAC)
Physical Layer Interface (PHY)
Clock
Generator
Clock
Recovery
USB Event
Detect
Transceiver
VReg
D+ D-
Upstream Port
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS™ and MICROWIRE™ are trademarks of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
CLKOUT
V3.3
AGND
www.national.com
1 page  
A Disabled endpoint does not respond to IN, OUT, or 4.0 Connection Diagram
SETUP tokens.
The Endpoint Pipe Controller maintains separate status
and control information for each endpoint pipe.
For IN tokens, the Endpoint Pipe Controller is responsible
for transferring data from the defined buffer to the host.
For OUT tokens, the Endpoint Pipe Controller is responsi-
ble for transferring data from the host to the defined buffer.
3.5 Microcontroller Interface
CS
RD
WR/SK
INTR
DRQ
1
2
3
4
5
A CPU or microcontroller can be connected via an 8-bit
parallel interface or a MICROWIRE interface. For the par-
allel interface, there are two addressing modes (multi-
plexed or non-multiplexed). These modes are selected by
hardwiring the proper binary code on the MODE1 and
MODE0 pins.
In addition, an interrupt output is provided. The type of the
interrupt can be programmed to be either push-pull active-
high or active-low output, or an open-drain active-low out-
put.
DACK
A0/ALE/SI
D0/SO
D1
D2
D3
D4
D5
D6
6
7
8
9
10
11
12
13
14
28 pin
SO
28 CLKOUT
27 XOUT
26 XIN
25 MODE0
24 MODE1
23 GND
22 Vcc
21 GND
20 D–
19 D+
18 V3.3
17 AGND
16 RESET
15 D7
Order Number USBN9602-28M
See NS Package Number M28B
Figure 1. USBN9602 Connection Diagram
5 www.national.com
5 Page 
6.0 Parallel Interface (Continued)
CS
WR
RD
AD[7:0]
ALE
DATA IN 0x00
DATA OUT
ADDR
EN
ADDRESS 0x3F
REGISTER FILE
Figure 6. Multiplexed Mode Interface Block Diagram
ALE
CS
RD or WR
AD[7:0]
ADDR
DATA
Figure 7. Multiplexed Mode Basic Read/Write Timing
11 www.national.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet USBN9602.PDF ] | |
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