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Número de pieza | UPG153TB-E3 | |
Descripción | L-BAND SPDT SWITCH | |
Fabricantes | NEC | |
Logotipo | ||
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No Preview Available ! DATA SHEET
GaAs INTEGRATED CIRCUIT
µPG153TB
L-BAND SPDT SWITCH
DESCRIPTION
The µPG153TB is an L-band SPDT (Single Pole Double Throw) GaAs FET switch which was developed for digital
cellular or cordless telephone application. The device can operate from 100 MHz to 2.5 GHz, having the low
insertion loss. It housed in an original 6-pin super minimold package that is smaller than usual 6-pin minimold easy
to install and contributes to miniaturizing the system.
FEATURES
• Low Insertion Loss : LINS = 0.7 dB TYP. @VCONT = +3.0 V/0 V, f = 2 GHz
• High Linearity Switching: Pin (1 dB) = +33.0 dBm TYP. @VCONT = +3.0 V/0 V, f = 2 GHz
• Small 6-pin super minimold package (Size: 2.0 × 1.25 × 0.9 mm)
APPLICATIONS
• L, S-band digital cellular or cordless telephone
• PCS, WLAN, and WLL applications
ORDERING INFORMATION
Part Number
µPG153TB-E3
Marking
G1J
Package
6-pin super minimold
Supplying Form
Embossed tape 8 mm wide.
Pin 1, 2, 3 face to tape perforation side.
Qty 3 kp/reel.
Remark To order evaluation samples, please contact your local NEC sales office. (Part number for sample
order: µPG153TB)
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Control Voltage 1, 2
Input Power
Total Power Dissipation
Operating Temperature
Storage Temperature
Symbol
VCONT1, 2
Pin
Ptot
TA
Tstg
Ratings
–6.0 to +6.0Note
+33
0.15
–45 to +85
–55 to +150
Unit
V
dBm
W
°C
°C
Note Condition 2.5 ≤ | VCONT1 – VCONT2 | ≤ 6.0 V
Remarks 1. Mounted on a 50 × 50 × 1.6 mm double copper clad epoxy glass PWB, TA = +85°C
2. Operation in excess of any one of these parameters may result in permanent damage.
Caution The IC must be handled with care to prevent static discharge because its circuit is composed of
GaAs MES FET.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. P13632EJ2V0DS00 (2nd edition)
Date Published September 1999 N CP(K)
Printed in Japan
The mark shows major revised points.
© 1998, 1999
1 page µPG153TB
TEST CIRCUIT
TA = +25°C, VCONT1 = +3 V, VCONT2 = 0 V or VCONT1 = 0 V, VCONT2 = +3 V, f = 2 GHz, ZO = 50 Ω
Off chip DC blocking capacitors value: C0 = 51 pF, C1 = 1 000 pF (Bypass), using NEC standard evaluation board
OUT1
OUT2
EVALUATION BOARD
C0 C0
123
G1J
6
C1
54
C1
C0
VCONT1
IN VCONT2
OUT1
OUT2
VCONT1
VCONT2
IN
Data Sheet P13632EJ2V0DS00
5
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet UPG153TB-E3.PDF ] |
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