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PDF UPF01002 Data sheet ( Hoja de datos )
| Número de pieza | UPF01002 | |
| Descripción | 10 Gigabit/s Ethernet Transceiver with OC-192c Framer and XAUI Interface | |
| Fabricantes | Infineon Technologies | |
| Logotipo |  |
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PRODUCT BRIEF
10 Gigabit/s Ethernet Trans-
ceiver with OC-192c Framer
and XAUI Interface
The TenGiPHY-W is a single chip transceiver IC
for 10 Gbit/s Ethernet and Fibre Channel connec-
tivity. It offers a serial, full duplex 10 Gbit/s inter-
face to an optical sub-module. The integrated
CDR and CMU operate at data rates between
9.95328 and 10.51875Gbit/s. The TenGiPHY-W pro-
vides the XGXS, PCS and PMA sublayers of the
10G Ethernet and Fibre Channel standards. For
WAN applications a standard OC-192/STM-64
SONET/SDH framer together with flexible clocking
modes enables a direct connection to the public
network without additional components.
The networking system can control the chip via a
narrow-width MDIO interface by writing and read-
ing its control and status registers.
Applications
■ Fiber optic modules according to
the XENPAK multi-source
agreement
■ 10 Gbit/s Ethernet and Fibre
Channel line cards
■ Ethernet backbones in Metro
Area Networks
■ Terabit Routers
Features
■ Complete 10 Gbit/s Ethernet and
Fibre Channel PHY supporting
WAN and LAN applications
■ Complies with IEEE 802.3ae
■ Compliant to XENPAK multi-
source agreement
■ Complies with ANSI 1413-D
■ Embedded µController allows for
control and tuning of the PMDs
via analog interfaces
■ Clock & data recovery and clock
multiplying unit without external
loop filter components
UPF 01002■ Complies with jitter tolerance
and jitter transmit requirements
■ Performance monitoring accord-
ing to ANSI T1. 231
according to Telcordia GR-1244- ■ Various loop back modes for
CORE and ITU-T G.825
system debugging
■ Supports various clocking
modes based on external refer-
ence clocks, loop- and external
timing
■ Provides access to E²PROM via
I²C interface according to XEN-
PAK requirements; automatic
E²PROM download on power-up
■ Integrated bit error rate tester
(BERT) usable for multiple at-
speed diagnostic scenarios
■ Power-efficient design:
<1.3W @ 1.3V
■ Includes the XGXS, PCS, WIS,
and PMA sublayers of the OSI
protocol stack
■ Synchronization and de-skewing
of XAUI lanes
■ Integrated standard STS-192/
STM-64 SONET/SDH framer
according to GR-253-CORE,
ANSI T1. 105/416, ITU-T G.707.
■ Optionally maps/extracts
10 Gbit/s Ethernet packets into/
from the STS-192c/VC4-64c
payload or conveys them to the
Interfaces
■ Full duplex, XFI compliant serial
CML line interface for data rates
between 9.95 and 10.5 Gbit/s
■ Quad serial Gbit/s XAUI interface
with data rates between 3.1 and
3.2 Gbit/s
■ MDIO interface
■ I²C bus interface
■ XENPAK diagnostic interface
providing eight 12-bit ADCs and
four 10-bit DACs
serial interface directly
■ IEEE 1149.1 JTAG boundary
scan interface
UPF 01002
TenGiPHY-W
Never stop thinking.
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