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PDF UPD98411 Data sheet ( Hoja de datos )
| Número de pieza | UPD98411 | |
| Descripción | ATM QUAD SONET FRAMER | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD98411
ATM QUAD SONET FRAMER
The µPD98411 NEASCOT-P40 is one of ATM-LAN LSIs and provides the functions of the TC sublayer of the
SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum. Its main functions include a
transmission function to map an ATM cell passed from an ATM layer to the payload of 155M-bps SONET STS-
3c/SDH STM-1 frame and transmit the cell to the PMD (Physical Media Dependent) sublayer of the physical layer,
and a reception function to separate the overhead and ATM cell from the data string received from the PMD device
and transmit the ATM cell to the ATM layer. The µPD98411 NEASCOT-P40 combines these transmission
/reception functions into a port function that is realized as a single 4-port LSI chip. This LSI is ideally suited for
use in the ATM hubs, ATM switches, and other equipment used to configure an ATM network.
In addition, the µPD98411 also has a clock recovery function for each port to extract synchronous clock for
reception of receive data from the bit stream, and a clock synthesis function to generate a clock for transmission.
For the details of functional description, refer to the following user's manual.
µPD98411 User's Manual : S12736E
FEATURES
• Incorporates an ATM user network interface TC sublayer function for four channels.
• Conforms to ATM FORUM UNI v3.1.
• Incorporates four clock recovery PLLs and one clock synthesizer PLL.
• Conforms to ATM FORUM UTOPIA Level 2 v1.0.
• ATM layers can be selected from the multi-PHY interface (up to 800 Mbps) in several different modes.
Single 16-bit
Single 8-bit
Dual 8-bit
1TCLAV/1RCLAV (Cell Available signal mode)
Direct Status Indication mode
Multiplexed Status Polling mode
• A management interface can be set to either of two modes.
RD-WR-RDY style (Intel-compatible mode)
DS-R/W-ACK style (Motorola-compatible mode)
• The line-side PMD interface accepts a P-ECL level input.
• Supports a loopback function.
• Supports a pseudo error generation frame transmission function.
• Incorporates one general input port per channel and three output ports (each able to drive an LED) per
channel.
• Supports JTAG boundary scan test (IEEE 1149.1).
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S12953EJ4V0DS00 (4th edition)
Date Published January 1999 NS CP(K)
Printed in Japan
©NEC Corporation 1997,1999
1 page  
µPD98411
3) UTOPIA Interface
The UTOPIA interface transfers transmit/receive cell data to a device in the upper ATM layer. The interface
between the µPD98411 and the ATM layer conforms to “MPHY Data Path Operation” of the “UTOPIA Level 2
version 1.0 June ’95” standard.
Bus Mode
The way to indicate Cell Available state
Dual eight-bit bus.
One TCLAV & one RCLAV signal mode
In this mode, an 8-bit data bus is used for two ports. Ports 0 The one TCLAV & one RCLAV signal mode outputs the TCLAV
and 1 transfer signals using one eight-bit bus, while ports 2 and RCLAV signal status information for four ports of the
and 3 transfer signals using another eight-bit bus. The ports µPD98411 by multiplexing them into a single signal.
operate independently.
PMD µPD98411
UTOPIA
µPD98411
Port0
Port1
Port2
Port3
8-bit
ATM layer
device
8-bit
ATM layer
device
Port0
Port1
Port2
Port3
TCLAV
RCLAV
TDI
8 or 16-bit
RDO
TADD
ATM layer
Device
RADD
Single eight-bit bus.
In this mode, cell data for all four ports is transferred through
an eight-bit bus. The maximum transfer rate is 400 Mbps
(8 bits x 50 MHz).
Direct Status Indication Mode
µPD98411 has four TXCLAV and RXCLAV status signals, one
pair of TXCLAV and RXCLAV for each port. Status signals and
cell transfers are independent of each other. No address
information is needed to obtain status information.
PMD
µPD98411
Port0
UTOPIA
Port0
TCLAV3-TCLAV0
Port1
Port2
Port3
8-bit ATM layer
device
Port1
µPD98411
Port2
Port3
RCLAV3-RCLAV0
TDI
8 or 16-bit
RDO
TADD
RADD
ATM layer
Device
Single sixteen-bit bus.
In this mode, cell data for all four ports is transferred through
a sixteen-bit bus. The maximum transfer rate is 800 Mbps
(16 bits x 50 MHz).
Multiplexed Status Polling Mode
When six or more µPD98411s are connected to one ATM layer,
ATM layer obtain the status information of all the connected
ports in the 53 clock cycles in which it transmits or receives a
PMD
µPD98411
UTOPIA
single data cell. Because a minimum of two clock cycles are
required to obtain the TCLAV/RCLAV signal status of a port by
Port0
ATM layer polling. Therefore every port address is allocated in a
Port1
Port2
16-bit
ATM layer
device
fixed manner to one of the four status signals and to one of eight
port groups.
Port3
Data Sheet S12953EJ4V0DS00
5
5 Page 
µPD98411
PIN NAME
ACK/RDY_B
BMODE
CMD3-CMD0
CS_B
CSSEL
DS/RD_B
GND
GND-CS
GND-PE3,
GND-PE2,
GND-PE1,
GND-PE0
GND-PEC
JCK
JDI
JDO
JMS
JRST_B
MADD[8:0]
MD[7:0]
PALM3[2:0],
PALM2[2:0],
PALM1[2:0],
PALM0[2:0]
: Acknowledge/Ready
: Bus Mode
: Command Signal
: Chip Select
: Clock Source Select
: Data Strobe/Read
: Ground
: Ground for Analog PLL Block
: Ground for Rx PECL Block
: Ground for TFKT/C PECL Block
: JTAG Clock
: JTAG Data Input
: JTAG Data Output
: JTAG Mode Select
: JTAG Reset
: Management Interface Address
Bus
: Management Interface Data Bus
: Physical Alarm Output Signals
PHINT3_B,
PHINT2_B,
PHINT1_B,
PHINT0_B,
: Physical Interrupt
RADD2[4:0],
RADD1[4:0]
: Receive Address
RCL
: Internal Receive System Clock
RCLAV3-RCLAV0 : Receive Cell Available Signals
RCLK2, RCLK1
RDIC3-RDIC0
RDIT3-RDIT0
: Receive Data Transferring Clock
: Receive Data Input Complement
: Receive Data Input True
RDO[15:0]
: Receive Data Output
REFCLK
: System Clock
REFCLK-2nd : 2nd Reference Cock
RENBL2_B,
: Receive Data Enable
RENBL1_B
RESET_B
: System Reset
RPR2, RPR1 : Receive Data Path Parity
RSOC2, RSOC1 : Receive Start Of Cell
RW/WR_B
: Management Interface Read/Write
RxFP
: Receive Frame Pulse
SD3-SD0
: Signal Detect
TADD2[4:0],
: Transmit Address
TADD1[4:0]
TCL : Internal Transmit System Clock
TCLAV3-TCLAV0 : Transmit Cell Available Signals
TCLK2, TCLK1 : Transmit DATA transferring Clock
TDI15-TDI0
: Transmit Data Input from the ATM
Layer
TDOC3-TDOC0 : Transmit Data Output Complement
TDOT3-TDOT0 : Transmit Data Output True
TENBL2_B,
: Transmit Data Enable
TENBL1_B
TFKC
: Transmit Reference Clock Complement
TFKT
: Transmit Reference Clock True
TFSS
: Transmit Frame Set Signal
TPR2,TPR1
TSOC2,TSOC1
TxFP
VDD
VDD-CS
: Transmit Data Path Parity
: Transmit Start Of Cell
: Transmit Frame Pulse
: Supply Voltage
: Supply Voltage for Analog PLL Block
VDD-PE3,
VDD-PE2,
VDD-PE1,
VDD-PE0
: Supply Voltage for Rx PECL Block
VDD-PEC
XLFC
: Supply Voltage for TFKT/C PECL
Block
: Tx Loop Filter Capacity
Data Sheet S12953EJ4V0DS00
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD98411.PDF ] | |
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