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PDF UPD98409 Data sheet ( Hoja de datos )
| Número de pieza | UPD98409 | |
| Descripción | ATM LIGHT SAR CONTROLLER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD98409
ATM LIGHT SAR CONTROLLER
DESCRIPTION
The µPD98409 (NEASCOT-S40CTM) is a high-performance SAR chip for segmentation and reassembly of ATM
cells. Provided with a PCI (Peripheral Component Interconnect) bus interface control memory and supporting a
MPEG packet transfer engine function to mitigate the workload of the CPU in transferring compressed image data,
this chip has ideal specifications for use in a set top box (STB) to interface with an ATM network. The µPD98409
conforms to ATM Forum recommendations and has AAL5-SAR sublayer and ATM layer functions.
FEATURES
• Conforms to ATM Forum
• PCI bus interface (5/3.3 V, 32/64 bits, 33 MHz)
Conforms to PCI Local Bus Specification Revision 2.1
• AAL-5 SAR sublayer and ATM layer functions
• Hardware support of AAL-5 processing (non-AAL-5 processing can be supported in software)
• Supports up to 64 virtual channels (VC) (64-VC control memory)
• Two traffic shapers for transmission scheduling
• MPEG packet transfer engine mitigating the workload of compressed image data transfer by CPU
• Receive FIFO of 12 cells
• PHY device I/F: UTOPIA Level-1 interface (octet/cell level handshake)
• JTAG boundary scan test functions
• 0.35-µm CMOS process, +5/+3.3-V power supply
- Bus interface +5 V : +5/+3.3-V power supply
- Bus interface +3.3 V : +3.3-V single power supply
ORDERING INFORMATION
Part Number
µPD98409GN-LMU
Package
240-pin plastic QFP (0.5-mm fine pitch) (32 × 32 mm)
The information in this document is subject to change without notice.
Document No. S12775EJ2V0DS00 (2nd edition)
Date Published May 1998 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1997, 1998
1 page  
µPD98409
CONTENTS
1. PIN FUNCTION ...................................................................................................................................... 6
1.1 PHY Device Interface Pin............................................................................................................................... 6
1.1.1 UTOPIA interface................................................................................................................................. 6
1.1.2 PHY device control interface ............................................................................................................. 7
1.2 Bus Interface Pins.......................................................................................................................................... 8
1.3 Serial EEPROM Interface Pins .................................................................................................................... 10
1.4 JTAG Boundary Scan Pins.......................................................................................................................... 10
1.5 Other Pins..................................................................................................................................................... 11
1.6 Power and Ground Pins .............................................................................................................................. 11
2. ELECTRICAL SPECIFICATIONS ........................................................................................................ 12
3. PACKAGE DRAWING ......................................................................................................................... 33
4. SOLDERING CONDITIONS ................................................................................................................. 34
5
5 Page 
µPD98409
1.5 Other Pins
Pin Name
PHYSEL1
Pin No.
225
I/O
I
PO3-PO0
192 - 195
O
LA5-LA0
LASTB
182 - 185,
187, 188
189
O
O
I/O Level
LV-TTL
CMOS
TTL
TTL
Function
Internal test pin.
Input a low level to this pin.
General-purpose output port.
General-purpose output port pins. These pins output the value written to
the GPOR register.
Internal test pins.
Leave these pins open during normal operation.
Internal test pin.
Leave this pin open during normal operation.
1.6 Power and Ground Pins
Pin Name
VDD3
VDD5
Pin No.
21, 40, 61, 81, 91, 100, 120,
130, 140, 151, 160, 169, 181,
190, 201, 206, 220, 240
8, 14, 32, 47, 52, 58, 67, 76,
234, 237
I/O
GND
1, 2, 7, 12, 15, 20, 26, 31, 36,
41, 46, 53, 59, 60, 66, 70, 72,
74, 77, 78, 80, 85, 90, 96, 98,
101, 110, 112, 121, 122, 127,
129, 137, 139, 145, 150, 156,
161, 168, 174, 179, 180, 186,
191, 196, 200, 207, 213, 215,
221, 223, 228, 233, 236
Function
+3.3-V power supply.
These pins supply +3.3 V to the chip.
+5 V power supply.
These pins supply +5 V to the chip when a +5-V bus interface is used.
Supply +3.3 V to these pins when a +3.3-V bus interface is used.
Ground.
Connect to ground.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD98409.PDF ] | |
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