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PDF UPD75P218 Data sheet ( Hoja de datos )

Número de pieza UPD75P218
Descripción 4-BIT SINGLE-CHIP MICROCOMPUTER
Fabricantes NEC 
Logotipo NEC Logotipo



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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P218
4-BIT SINGLE-CHIP MICROCOMPUTER
The µPD75P218 is a one-time PROM version that can be written to only once or an EPROM version that allows
program writing, erasing, and rewriting, of the µPD75218 Note.
Since the program can be written by the user, the µPD75P218 is suitable for preproduction use during
system development, or limited production.
Read this material together with the µPD75218 materials.
Note Under development
FEATURES
µPD75218 compatible
On-chip 16K-byte mode/32K-byte mode switching function
Operates at the same power supply voltage range (2.7 to 6.0 V) as the mask ROM version µPD75218.
32640 × 8 bits of PROM
1024 × 4 bits of RAM
No pull-down resistor for Port 6
High breakdown voltage display output
• S0 to S8, T0 to T9 : On-chip pull-down resistor
• S9, T10 to T15 : Open drain
No power-on reset circuit
Caution No mask-option pull-down resistor is provided.
ORDERING INFORMATION
Part Number
µPD75P218CW
µPD75P218GF-3BR
µPD75P218KB
Package
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14 × 20 mm)
64-pin ceramic LCC with window (14 × 20 mm)
Quality Grade
Standard
Standard
Standard
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The word “PROM” in this document refers to the common parts of the one-time PROM products and
EPROM products.
Document No. IC-2541A
(O.D. No. IC-7962A)
Date Published March 1993 P
Printed in Japan
The information in this document is subject to change without notice.
© NEC CORPORATIO1N981991

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UPD75P218 pdf
µPD75P218
1.2 NON-PORT PINS
Pin name
T0 - T9
T10/S15 -
T13/S12
T14/S11,
T15/S10
S9
S0 - S8
PPO
TI0
SCK
SO
SI
INT4
INT0
INT1
INT2
BUZ
X1, X2
XT1, XT2
RESET
MD0 - MD3
VPP
VLOAD
VDD
VSS
NC Note 3
Input/
output
Output
Output
Input
I/O
I/O
Input
Input
Input
Input
I/O
Input
I/O
Shared
pin
PH3 - PH0
P13
P01
P02
P03
P00
P10/VPP
P11
P12
P23
P30 - P33
P10/INT0
Function
When reset
Note 1
High breakdown voltage large current output pin
for digit output
Note 2
High breakdown voltage large current output pin
for digit/segment output
The remainder of the pins can be used as PORTH.
High breakdown voltage large current output pin
for digit/segment output
Static output is also available.
High breakdown voltage output pin for segment
output
Static output is also available.
Note 1
High breakdown voltage output pin for segment
output
Output for receiving pulse signal for timer/pulse generator
Input for receiving external event pulse signal for timer/
event counter
Serial clock I/O
Serial data output or serial data I/O
Serial data input or normal input
Edge detection vectored interrupt input
(either rising edge or falling edge detection)
Edge detection vectored interrupt input with noise elimination
(detection edge selectable)
Low level
High
impedance
Low level
High
impedance
Input
Input
Input
Edge detection testable input (rising edge detection)
Fixed frequency output pin (for buzzer or system clock trimming)
Crystal/ceramic resonator connection for main system clock
generation.
When external clock is used, it is applied to X1, and its
reserve phase signal is applied to X2.
Crystal connection for subsystem clock generation.
When external clock is used, it is applied to XT1, and XT2 is open.
System reset input (low level active)
Operation mode selection pins during the PROM write/verify cycles
+12.5 V is applied as the programming voltage during the
PROM write/verify cycles
Pull-down resistor connection pin of FIP® controller/driver
Positive power supply. +6 V is applied as the programming
voltage during the PROM write/verify cycles
GND potential
No connection
Input
Note 1. On-chip pull-down resistor
2. Open drain output
3. When using a printed board with a µPD75216A, 75217, or 75218, connect the NC pin to the VPRE.
5

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UPD75P218 arduino
µPD75P218
3.2 16K-BYTE MODE AND 32K-BYTE MODE SWITCHING
16K-byte mode and 32K-byte mode are switched by the stack bank selection register. The stack bank selection
register format is shown in Fig. 3-1.
The stack bank selection register is set by 4-bit memory manipulation instruction. RESET input sets bit 3 of the
stack bank selection register to “1” and changes from 32K-byte mode to 16K-byte mode. When 16K-byte mode is
used, manipulating the stack bank selection register is unnecessary. When 32K-byte mode is used, the stack bank
selection register must always be initialized to 00××B Note 1 at the beginning of the program.
Fig. 3-1 Stack Bank Selection Register Format
Address
F84H
321 0
SBS3 SBS2 SBS1 SBS0
Symbol
SBS
Stack area specification
0 0 Memory bank 0
0 1 Memory bank 1
1 0 Memory bank 2
1 1 Memory bank 3
0 Be sure to write 0 to bit 2.
Mode change specification
0 32K-byte mode
1 16K-byte mode Note 2
Caution When using 32K-byte mode, execute a subroutine call instruction and an interrupt enable instruc-
tion after the stack bank selection register is set after RESET input.
Notes 1. Set the desired value in ××.
2. When the 16K-byte mode is used after RESET input, the stack bank selection register does not have
to be manipulated.
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