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PDF UPD75P0116GB-3BS-MTX Data sheet ( Hoja de datos )
| Número de pieza | UPD75P0116GB-3BS-MTX | |
| Descripción | 4-BIT SINGLE-CHIP MICROCONTROLLER | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P0116
4-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD75P0116 replaces the µPD750108’s internal mask ROM with a one-time PROM and features expanded
ROM capacity.
Because the µPD75P0116 supports programming by users, it is suitable for use in prototype testing for system
development using the µPD750104, 750106, or 750108 products, and for use in small-lot production.
Detailed information about product features and specifications can be found in the following document
µPD750108 User's Manual: U11330E
FEATURES
• Compatible with µPD750108
• Memory capacity:
• PROM : 16384 × 8 bits
• RAM : 512 × 4 bits
• Can operate in same power supply voltage as the mask ROM version µPD750108
• VDD = 1.8 to 5.5 V
ORDERING INFORMATION
Part number
µPD75P0116CU
µPD75P0116GB-3BS-MTX
Package
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)
ROM (× 8 bits)
16384
16384
Caution On-chip pull-up resistors by mask option cannot be provided.
The information in this document is subject to change without notice.
Document No. U12603EJ1V0DS00 (1st edition)
Date Published June 1997 N
Printed in Japan
©
1997
1 page  
µPD75P0116
PIN NAMES
BUZ
CL1, CL2
D0-D7
INT0, 1, 4
INT2
KR0-KR7
MD0-MD3
NC
P00-P03
P10-P13
P20-P23
P30-P33
P40-P43
P50-P53
P60-P63
: Buzzer Clock
: Main System Clock (RC)
: Data Bus 0-7
: External Vectored Interrupt 0, 1, 4
: External Test Input 2
: Key Return 0-7
: Mode Selection 0-3
: No Connection
: Port0
: Port1
: Port2
: Port3
: Port4
: Port5
: Port6
P70-P73
P80, P81
PCL
PTO0, PTO1
RESET
SB0, SB1
SCK
SI
SO
TI0
VDD
VPP
VSS
XT1, XT2
: Port7
: Port8
: Programmable Clock
: Programmable Timer Output 0, 1
: Reset
: Serial Data Bus 0, 1
: Serial Clock
: Serial Input
: Serial Output
: Timer Input 0
: Positive Power Supply
: Programming Power Supply
: Ground
: Subsystem Clock (Crystal)
5
5 Page 
µPD75P0116
3.4 Handling of Unused Pins
Table 3-1. Handling of Unused Pins
Pin
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
P10/INT0-P12/INT2
P13/TI0
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ
P30/MD0-P33/MD3
P40/D0-P43/D3
P50/D4-P53/D7
P60/KR0-P63/KR3
P70/KR4-P73/KR7
P80, P81
XT1Note
XT2Note
VPP
Recommended connection
Connect to VSS or VDD
Individually connect to VSS or VDD via resistor
Connect to VSS
Connect to VSS or VDD
Input mode : individually connect to VSS or VDD
via resistor
Output mode : open
Connect to VSS
Input mode : individually connect to VSS or VDD
via resistor
Output mode : open
Connect to VSS or VDD
Open
Make sure to connect directly to VDD
Note When the subsystem clock is not used, set SOS. 0 to 1 (not to use the internal feedback resistor).
11
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