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PDF UPD75238 Data sheet ( Hoja de datos )
| Número de pieza | UPD75238 | |
| Descripción | 4 BIT SINGLE-CHIP MICROCOMPUTER | |
| Fabricantes | NEC | |
| Logotipo |  |
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ELECTRON DEVICE
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75238
4 BIT SINGLE-CHIP MICROCOMPUTER
The µPD75238 is a single-chip microcomputer which contains a CPU capable of 1-, 4-, and 8-bit data
processing, ROM, RAM, and I/O ports. In addition, it contains a fluorescent display tube (FIP;) controller/driver,
A/D converter, clock timer, timer/pulse generator capable of 14-bit PWM output, serial interface, and vectored
interrupt function.
In comparison with the µPD75217, the µPD75238 has larger ROM and RAM capacity and has been enhanced
in such peripheral facilities as the display function of the FIP controller/driver, I/O ports, A/D converter, serial
interface.
The µPD75238 finds best use in such applications as timer/tuner of VCRs from advanced type to common
type, configuration of one-chip system control microcomputer, advanced CD player, advanced microwave
ovens, etc.
With the µPD75238, the µPD75P238, which is a PROM product, and various development tools including
IE-75001-R and assemblers are available. They can be used for evaluation during system development and
small-volume production.
FEATURES
• Mass-storage built-in ROM and RAM
• Program memory (ROM) : 32K × 8
• Data memory (RAM) : 1K × 4
• I/O port: 64 lines (excluding pins dedicated
to FIP)
• Minimum instruction execution time:
0.67 µs (at 6.0 MHz)
• Instruction execution time specification func-
tion to allow a wide range of operating
voltages
• Programmable FIP controller/driver contained
• Number of segments: 9 to 24 segments
• Number of digits : 9 to 16 digits
• 8-bit A/D converter: 8 channels
• Enhanced timer/counter function: 5 channels
• 8-bit serial interface: 2 channels
• Application-oriented interrupt functions
• PROM version device: µPD75P238
ORDERING INFORMATION
Part number
µPD75238GJ-×××-5BG
Package
94-pin plastic QFP (20 × 20 mm)
Quality grade
Standard
Please refer to “Quality Grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
Document No.
(O.D. No.
Date Published
Printed in Japan
IC-2777A
IC-8177A)
February 1993 P
The information in this document is subject to change without notice.
Major changes in this revision are indicated by stars (5) in the margins.
© NEC Corporation 1992
1 page  
CONTENTS
µPD75238
1. PIN FUNCTIONS ........................................................................................................................
1.1 PORT PINS ......................................................................................................................................
1.2 NON-PORT PINS ............................................................................................................................
1.3 PIN INPUT/OUTPUT CIRCUITS ....................................................................................................
1.4 CONNECTION OF UNUSED µPD75238 PINS ..............................................................................
7
7
9
11
15
2. ARCHITECTURE AND MEMORY MAP OF THE µPD75238 ................................................... 16
2.1 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES ................................ 16
2.2 GENERAL REGISTER BANK CONFIGURATION .......................................................................... 19
2.3 MEMORY-MAPPED I/O ................................................................................................................. 22
3. INTERNAL CPU FUNCTIONS .................................................................................................... 27
3.1 PROGRAM COUNTER (PC) ........................................................................................................... 27
3.2 PROGRAM MEMORY (ROM) ........................................................................................................ 27
3.3 DATA MEMORY (RAM) ................................................................................................................. 29
3.4 GENERAL REGISTERS ................................................................................................................... 31
3.5 ACCUMULATORS .......................................................................................................................... 32
3.6 STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) ..................................... 32
3.7 PROGRAM STATUS WORD (PSW) .............................................................................................. 35
3.8 BANK SELECT REGISTER (BS) ..................................................................................................... 39
4. PERIPHERAL HARDWARE FUNCTIONS .................................................................................. 40
4.1 DIGITAL I/O PORTS ....................................................................................................................... 40
4.2 CLOCK GENERATOR ...................................................................................................................... 49
4.3 CLOCK OUTPUT CIRCUIT ............................................................................................................. 58
4.4 BASIC INTERVAL TIMER ............................................................................................................... 61
4.5 TIMER/EVENT COUNTER ............................................................................................................. 63
4.6 CLOCK TIMER ................................................................................................................................. 69
4.7 TIMER/PULSE GENERATOR ......................................................................................................... 71
4.8 EVENT COUNTER .......................................................................................................................... 77
4.9 SERIAL INTERFACE ....................................................................................................................... 79
4.10 A/D CONVERTER ........................................................................................................................... 113
4.11 BIT SEQUENTIAL BUFFER ............................................................................................................ 119
4.12 FIP CONTROLLER/DRIVER ............................................................................................................ 119
5. INTERRUPT FUNCTION ............................................................................................................ 131
5.1 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT .................................................... 131
5.2 HARDWARE OF THE INTERRUPT CONTROL CIRCUIT .............................................................. 133
5.3 INTERRUPT SEQUENCE ................................................................................................................ 138
5.4 MULTIPLE INTERRUPT PROCESSING CONTROL ...................................................................... 139
5.5 VECTOR ADDRESS SHARE INTERRUPT PROCESSING ............................................................ 141
5
5 Page 
1.3 PIN INPUT/OUTPUT CIRCUITS (1/4)
Type A
VDD
P-ch
IN
N-ch
CMOS input buffer
Type B
µPD75238
Type D
Data
Output
disable
VDD
P-ch
OUT
N-ch
Push-pull output which can be set to high-impedance output
(off for both P-ch and N-ch)
Type E
IN
Schmitt trigger input with hysteresis
Type B - C
VDD
P.U.R.
P-ch
P.U.R.
enable
IN
P.U.R.: Pull-Up Resistor
Schmitt trigger input with hysteresis
Data
Output
disable
Type D
IN/OUT
Type A
I/O circuit consisting of a push-pull output
of type D and an input buffer of type A
Type E - B
Output
disable
VDD
P.U.R.
P-ch
Data
Output
disable
Type D
IN/OUT
Type A
P.U.R.: Pull-Up Resistor
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet UPD75238.PDF ] | |
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