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PDF UPD75236 Data sheet ( Hoja de datos )
| Número de pieza | UPD75236 | |
| Descripción | 4-BIT SINGLE-CHIP MICROCOMPUTER | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75236
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD75236 is a microcomputer with a CPU capable of 1-, 4-, and 8-bit-wise data processing, a ROM, a
RAM, I/O ports, a fluorescent display tube (FIP ®) controller/driver, A/D converters, a watch timer, a timer/pulse
generator capable of outputting 14-bit PWM, a serial interface and a vectored interrupt function integrated on a
single-chip.
The µPD75236 has the more improved peripheral functions including the RAM capacity, FIP controller/driver
display capabilities, I/O ports, A/D converter and serial interface than those of the µPD75216A.
The µPD75236 is most suited for advanced and popular VCR timer and tuner applications, single-chip
configurations of system computers, advanced CD players and advanced microwave ovens.
The µPD75P238 PROM product and various types of development tools (IE-75001-R, assemblers and others)
are available for evaluation in system development or small-volume production.
FEATURES
q Built-in, large-capacity ROM and RAM
• Program memory (ROM): 16K × 8
• Data memory (RAM): 768 × 4
q I/O port: 64 ports (except FIP dedicated pins)
q Minimum instruction execution time: 0.95 µs
(when operated at 4.19 MHz)
q Instruction execution time varying function to
achieve a wide range of power supply voltages
q Built-in programmable FIP controller/driver
• Number of segments: 9 to 24
• Number of digits: 9 to 16
q 8-bit A/D converter: 8 channels
q Powerful timer/counter function: 5 channels
q 8-bit serial interface: 2 channels
q Interrupt function with importance attached to
applications
q Product with built-in PROM: µPD75P238
ORDERING INFORMATION
Ordering Code
Package
Quality Grade
µPD75236GJ-×××-5BG
94-pin plastic QFP (20 × 20 mm)
Standard
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Document No. IC-2677A
(O. D. No. IC-8092A)
Date Published February 1993 P
Printed in Japan
The information in this document is subject to change without notice.
The mark 5 shows major revised points.
© NEC Corporation 1992
1 page  
µPD75236
CONTENTS
1. PIN FUNCTIONS ......................................................................................................................................... 7
1.1 PORT PINS ........................................................................................................................................................... 7
1.2 NON-PORT PINS .................................................................................................................................................. 9
1.3 PIN INPUT/OUPUT CIRCUIT LIST ................................................................................................................... 11
1.4 RECOMMENDED CONNECTIONS OF µPD75236 UNUSED PINS ............................................................... 15
2. µPD75236 ARCHITECTURE AND MEMORY MAP................................................................................ 16
2.1 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODE ..................................................... 16
2.2 GENERAL REGISTER BANK CONFIGURATION ............................................................................................ 19
2.3 MEMORY MAPPED I/O .................................................................................................................................... 22
3. INTERNAL CPU FUNCTIONS .................................................................................................................. 28
3.1 PROGRAM COUNTER (PC): 14 BITS .............................................................................................................. 28
3.2 PROGRAM MEMORY (ROM): 16256 WORDS × 8 BITS ............................................................................... 28
3.3 DATA MEMORY ................................................................................................................................................ 30
3.4 GENERAL REGISTER: 8 × 4 BITS × 4 BANKS ............................................................................................... 32
3.5 ACCUMULATOR ............................................................................................................................................... 33
3.6 STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) ....................................................... 33
3.7 PROGRAM STATUS WORD (PSW): 8 BITS ................................................................................................... 36
3.8 BANK SELECT REGISTER (BS) ....................................................................................................................... 40
4. PERIPHERAL HARDWARE FUNCTIONS ............................................................................................... 41
4.1 DIGITAL INPUT/OUTPUT PORTS ................................................................................................................... 41
4.2 CLOCK GENERATOR ........................................................................................................................................ 50
4.3 CLOCK OUTPUT CIRCUIT ................................................................................................................................ 58
4.4 BASIC INTERVAL TIMER ................................................................................................................................. 61
4.5 TIMER/EVENT COUNTER ................................................................................................................................ 63
4.6 WATCH TIMER .................................................................................................................................................. 69
4.7 TIMER/PULSE GENERATOR ........................................................................................................................... 71
4.8 EVENT COUNTER ............................................................................................................................................. 77
4.9 SERIAL INTERFACE .......................................................................................................................................... 79
4.10 A/D CONVERTER ........................................................................................................................................... 113
4.11 BIT SEQUENTIAL BUFFER: 16 BITS ............................................................................................................. 119
4.12 FIP CONTROLLER/DRIVER ............................................................................................................................ 119
5. INTERRUPT FUNCTIONS ...................................................................................................................... 131
5.1 INTERRUPT CONTROL CIRCUIT CONFIGURATION ................................................................................... 131
5.2 INTERRUPT CONTROL CIRCUIT HARDWARE DEVICES ........................................................................... 133
5.3 INTERRUPT SEQUENCE ................................................................................................................................ 138
5.4 MULTI-INTERRUPT SERVICE CONTROL ..................................................................................................... 139
5.5 VECTOR ADDRESS SHARING INTERRUPT SERVICING ........................................................................... 141
6. STANDBY FUNCTIONS ......................................................................................................................... 142
6.1 STANDBY MODE SETTING AND OPERATING STATE .............................................................................. 142
6.2 STANDBY MODE RELEASE .......................................................................................................................... 144
6.3 OPERATION AFTER STANDBY MODE RELEASE ....................................................................................... 146
5
5 Page 
1.3 PIN INPUT/OUTPUT CIRCUIT LIST (1/4)
TYPE A
IN
VDD
P-ch
N-ch
CMOS-Specified Input Buffer
TYPE B
IN
Schmitt Trigger Input Having Hysteresis
Characteristics
TYPE B-C
VDD
P.U.R
P-ch
IN
P.U.R
enable
P.U.R:Pull-Up Resistor
Schmitt Trigger Input Having Hysteresis
Characteristics
µPD75236
TYPE D
data
output
disable
VDD
P-ch
OUT
N-ch
Push-Pull Output which can be Set to Output High
Impedance (with Both P-ch and N-ch Set to OFF)
TYPE E
data
output
disable
Type D
IN/OUT
Type A
Input/Output Circuit Consisting of Type D
Push-Pull Output and Type A Input Buffer
TYPE E-B
output
disable
data
output
disable
Type D
VDD
P.U.R
P-ch
IN/OUT
Type A
P.U.R:Pull-Up Resistor
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet UPD75236.PDF ] | |
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