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PDF UPD720122 Data sheet ( Hoja de datos )
| Número de pieza | UPD720122 | |
| Descripción | MOS Integrated Circuit | |
| Fabricantes | NEC | |
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DATA SHEET
MOS Integrated Circuit
µPD720122
USB2.0 Generic Device Controller
The µPD720122 is USB2.0 Generic Device Controller, which combines the NEC Electronics USB2.0 PHY and End-
point Controller. The Controller has certified by USB Implementers Forum. End-point Controller has banked two Bulk End-
point and one Interrupt End-point, and selectable three general CPU bus-types, suitable for designing various USB
device. The controller has the external local bus, that enables to perform high speed data transferring when CPU is
accessing to the controller. These IP Blocks in the controller are based completely on an NEC Electronics ASIC core, so
µPD720122 is suitable to design for the prototype system that are intended to design ASIC in the future.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
µPD720122 User’s Manual: S15829E
FEATURES
• Complaint with USB2.0 specification (Maximum data transferring rate: 480 Mbps)
• USB2.0 certified (TestID=40000822)
• High(480Mbps) / Full(12Mbps)- Speed support and switch automatically
• Easy to design NEC Electronics ASIC
• Generic USB2.0 Device Controller
• Two Bulk End-points and One Interrupt End-point
• Performed Data Local Bus independent from CPU bus.
(Maximum Data Transferring rate: 21 MBps with DMA mode )
• Selectable three CPU Bus Interface
ORDERING INFORMATION
Part Number
µPD720122GC-9EU
µPD720122F1-DN2
Package
100-pin plastic TQFP (Fine pitch) (14 × 14)
109-pin plastic FBGA (11 × 11)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16685EJ2V0DS00 (2nd edition)
Date Published June 2003 NS CP (K)
Printed in Japan
The mark shows major revised points.
2003
1 page  
µPD720122
µ PD720122GC-9EU
Pin Pin Name
No. Fucntion1
51 VDD
52 FM21
53 EP2_DRQB
54 EP2_DACKB
55 EP2_WRB
56 EP2_TCB
57 LD0
58 LD1
59 LD2
60 LD3
61 GND
62 LD4
63 LD5
64 LD6
65 LD7
66 LD8
67 LD9
68 GND
69 LD10
70 LD11
71 LD12
72 LD13
73 LD14
74 LD15
75 VDD
Pin Name
Function2
VDD
FM21
EP2_DRQB
EP2_DACKB
EP2_WRB
EP2_TCB
LD0
LD1
LD2
LD3
GND
LD4
LD5
LD6
LD7
LD8
LD9
GND
LD10
LD11
LD12
LD13
LD14
LD15
VDD
Pin Name
Function3
VDD
FM21
EP2_DRQB
EP2_DACKB
Reserved
EP2_TCB
Reserved
Reserved
Reserved
Reserved
GND
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GND
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VDD
Pin
No.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin Name
Fucntion1
GND
BUNRI
RREF
AVSS(R)
AVDD
AVSS
RPU
VSS
RSDP
DP
VDD
DM
RSDM
VSS
NC
PVSS
NC
PVDD
VSS
VDD
VSS
M1
M0
VBUS
GND
Pin Name
Function2
GND
BUNRI
RREF
AVSS(R)
AVDD
AVSS
RPU
VSS
RSDP
DP
VDD
DM
RSDM
VSS
NC
PVSS
NC
PVDD
VSS
VDD
VSS
M1
M0
VBUS
GND
(2/2)
Pin Name
Function3
GND
BUNRI
RREF
AVSS(R)
AVDD
AVSS
RPU
VSS
RSDP
DP
VDD
DM
RSDM
VSS
NC
PVSS
NC
PVDD
VSS
VDD
VSS
M1
M0
VBUS
GND
Remark AVSS (R) should be used to connect RREF through 1 % precision reference resistor of 9.1 kΩ.
Data Sheet S16685EJ2V0DS
5
5 Page 
µPD720122
2. ELECTRICAL SPECIFICATIONS
2.1 Buffer List
• 3.3 V oscillator interface
XIN,XOUT
• 3.3 V input buffer
FM21,SCAN(1:0)
• 5V torelant input buffer
RESETB,CSB,A(7:0),WRB,RDB,ACTIVE,EP1_DACKB,EP1_RDB,EP1_TCB,EP2_DACKB,EP2_WRB,
EP2_TCB,BUNRI,M0,M1,VBUS,ALE
• 5V torelant output buffer
INTB_ALL,INT0B,INT1B,INT2B,M2,EP1_DRQB,EP2_DRQB
• 5V torelant I/O buffer
D(15:0),LD(15:0),AD(7:0),D0,AD(7:1),D(15:8)
• USB interface
DP,DM,RSDP,RSDM,RREF,RPU
2.2 Terminology
Terms Used in Absolute Maximum Ratings
Parameter
Symbol
Meaning
Power supply voltage
VDD Indicates voltage range within which damage or reduced reliability will not result
when power is applied to a VDD pin.
Input voltage
VI Indicates voltage range within which damage or reduced reliability will not result
when power is applied to an input pin.
Output voltage
VO Indicates voltage range within which damage or reduced reliability will not result
when power is applied to an output pin.
Output current
IO Indicates absolute tolerance value for DC current to prevent damage or reduced
reliability when a current flows out of or into an output pin.
Operating temperature
Storage temperature
TA
Tstg
Indicates the ambient temperature range for normal logic operations.
Indicates the element temperature range within which damage or reduced reliability
will not result while no voltage or current are applied to the device.
Data Sheet S16685EJ2V0DS
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD720122.PDF ] | |
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