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PDF V62C318256 Data sheet ( Hoja de datos )

Número de pieza V62C318256
Descripción 2.7 VOLT 32K X 8 STATIC RAM
Fabricantes Mosel Vitelic Corp 
Logotipo Mosel Vitelic  Corp Logotipo



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No Preview Available ! V62C318256 Hoja de datos, Descripción, Manual

MOSEL VITELIC V62C318256
2.7 VOLT 32K X 8 STATIC RAM
PRELIMINARY
Features
I High-speed: 35, 70 ns
I Ultra low DC operating current of 2mA (max.)
I Low Power Dissipation:
– TTL Standby: 0.5 mA (Max.)
– CMOS Standby: 10 µA (Max.)
I Fully static operation
I All inputs and outputs directly compatible
I Three state outputs
I Ultra low data retention current (VCC = 2V)
I Extended operating voltage: 2.7V–3.6V
I Packages
– 28-pin TSOP (Standard)
– 28-pin 300 mil SOP (450 mil pin-to-pin)
Description
The V62C318256 is a 262,144-bit static random
access memory organized as 32,768 words by 8
bits. It is built with MOSEL VITELIC’s high
performance CMOS process. Inputs and three-
state outputs are TTL compatible and allow for
direct interfacing with common system bus
structures.
Functional Block Diagram
A0 VCC
Row
Decoder
512 x 512
Memory Array
GND
A8
I/O0 Column I/O
Input
Data
Circuit
Column Decoder
I/O7
A9 A14
CE
OE
WE
Control
Circuit
318256 01
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
–40°C to +85°C
Package Outline
TF
••
••
Access Time (ns)
35 70
••
Power
L LL
••
Temperature
Mark
Blank
I
V62C318256 Rev. 1.7 July 2001
1

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V62C318256 pdf
MOSEL VITELIC
Data Retention Characteristics
Symbol
VDR
ICCDR
Parameter
VCC for Data Retention CE VCC 0.2V
Data Retention Current
VDR = 3.0V, CE VDR 0.2V
Coml
Ind.
tCDR
Chip Deselect to Data Retention Time
tR Operation Recovery Time (see Retention Waveform)
NOTES:
1. tRC = Read Cycle Time
2. TA = +25°C.
L
LL
L
LL
V62C318256
Min.
2.0
0
tRC(1)
Typ.(2)
1
0.5
Max.
3.6
40
10
45
15
Units
V
µA
ns
ns
Low VCC Data Retention Waveform
VCC
2.7V
tCDR
CE 2.2V
Data Retention Mode
VDR 2V
tR
CE VCC 0.2V
2.7V
2.2V
318256 06
V62C318256 Rev. 1.7 July 2001
5

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V62C318256 arduino
MOSEL VITELIC
Notes
V62C318256
V62C318256 Rev. 1.7 July 2001
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