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PDF V62C2802048LL-55T Data sheet ( Hoja de datos )
| Número de pieza | V62C2802048LL-55T | |
| Descripción | Ultra Low Power 256K x 8 CMOS SRAM | |
| Fabricantes | Mosel Vitelic Corp | |
| Logotipo |  |
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V62C2802048L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
• Low-power consumption
- Active: 35mA at 55ns
- Stand-by: 10 µA (CMOS input/output)
2 µA CMOS input/output, L version
• Single +2.2 to 2.7V Power Supply_Typical
• Extented Voltage from 2.2 to 3.6V.
• Equal access and cycle time
• 55/70/85/100 ns access time
• Easy memory expansion with CE1, CE2
and OE inputs
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
• Package available: 32L TSOP(I)/ STSOP(I)
• 48 Ball CSP_BGA
Functional Description
The V62C2802048L is a low power CMOS Static RAM
organized as 262,144 words by 8 bits. Easy memory exp-
ansion is provided by an active LOW CE1, an active
HIGH CE2, an active LOW OE, and Tri-state I/O’s. This
device has an automatic power-down mode feature when
deselected.
Writing to the device is accomplished by taking Chip
Enable 1 (CE1) with Write Enable (WE) LOW, and Chip
Enable 2 (CE2) HIGH. Reading from the device is per-
formed by taking Chip Enable 1 (CE1) with Output
Enable (OE) LOW while Write Enable (WE) and Chip
Enable 2 (CE2) is HIGH. The I/O pins are placed in a
high-impedance state when the device is deselected: the
outputs are disabled during a write cycle.
TheV62C2802048LL comes with a 1V data retention fe-
ature and Lower Standby Power. The V62C2802048L is
avalable in a 32-pin 8 x 20 mm TSOP1 / STSOP 8x13.4 mm
and CSP type 48-fpBGA packages.
Logic Block Diagram
32-Pin TSOP1 / STSOP (CSP_BGA See next page)
INPUT BUFFER
A0
A1
A2
A3
A4
A5 Cell Array
A6
A7
A8
A9
COLUMN DECODER
A10 A11 A12 A13 A14 A15 A16 A17
I/O8
I/O1
CONTROL
CIRCUIT
OE
WE
CE1
CE2
A11
A9
A8
A13
WE
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REV. 1.2 May 2001 V62C2802048L(L)
1
32 OE
31 A10
30 CE1
29 I/O8
28 I/O7
27 I/O6
26 I/O5
25 I/O4
24 GND
23 I/O3
22 I/O2
21 I/O1
20 A0
19 A1
18 A2
17 A3
1 page  
V62C2802048L(L)
Read Cycle (3,9) (Vcc = 2.2~2.7V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter
Symbol -55 -70 -85 -100 Unit Note
Read Cycle Time
Min Max Min Max Min Max Min Max
tRC
55 - 70 - 85 - 100 -
ns
Address Access Time
tAA - 55 - 70 - 85 - 100 ns
Chip Enable Access Time
tACE - 55 - 70 - 85 - 100 ns
Output Enable Access Time
tOE - 35 - 40 - 40 - 50 ns
Output Hold fromAddress Change
tOH
10 - 10 - 10 - 10
-
ns
Chip Enable to Output in Low-Z
tCLZ
10 - 10 - 10 - 10
-
ns 4,5
Chip Disable to Output in High-Z tCHZ - 25 - 30 - 35 - 40 ns 4,5
Output Enable to Output in Low-Z
tOLZ
5-5-5- 5
-
ns 4,5
Output Disable to Output in High-Z
tOHZ
- 25 - 25 - 30 - 35 ns 4,5
Power-Up Time
tPU
0-0-0- 0
-
ns
5
Power-Down Time
tPD
- 55 - 70 - 85 - 100 ns
5
Write Cycle (3,11) (Vcc = 2.2~2.7V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter
Write Cycle Time
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
Write Pulse Width
Write Recovering Time
Data Valid to Write End
Data Hold Time
Write Enable to Output in High-Z
Output Active from Write End
Symbol -55 -70 -85
-100 Unit Note
Min Max Min Max Min Max Min Max
tWC
55 - 70 - 85 - 100 -
ns
tCW
45 - 60 - 70 - 80
-
ns
tAW
45 - 60 - 70 - 80
-
ns
tAS
0-0-0- 0
-
ns
tWP
45 - 50 - 60 - 70
-
ns
tWR
0-0-0- 0
-
ns
tDW
25 - 30 - 35 - 40
-
ns
tDH
0-0-0- 0
-
ns
tWZ - 25 - 30 - 35 - 40 ns 4,5
tOW
5-5-5- 5
-
ns 4,5
REV. 1.2 May 2001 V62C2802048L(L)
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet V62C2802048LL-55T.PDF ] | |
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