V62C1801024LL-70T Datasheet PDF - Mosel Vitelic Corp
| Part Number | V62C1801024LL-70T | |
| Description | Ultra Low Power 128K x 8 CMOS SRAM | |
| Manufacturers | Mosel Vitelic Corp | |
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V62C1801024L(L)
Ultra Low Power
128K x 8 CMOS SRAM
Features
• Ultra Low-power consumption
- Active: 20mA at 70ns
- Stand-by: 5 µA (CMOS input/output)
1 µA CMOS input/output, L version
• Single +1.8V to 2.2V Power Supply
• Equal access and cycle time
• 70/85/100/150 ns access time
• Easy memory expansion with CE1 , CE2
and OE inputs
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
Functional Description
The V62C1801024L is a low power CMOS Static RAM or-
ganized as 131,072 words by 8 bits. Easy memory expansion
is provided by an active LOW CE1 , an active HIGH CE2, an
active LOW OE, and Tri-state I/O’s. This device has an a-
utomatic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip E-
nable 1 (CE1 ) with Write Enable (WE) LOW, and Chip Ena-
ble 2 (CE2) HIGH. Reading from the device is performed by
taking Chip Enable 1 (CE1) with Output Enable (OE)
LOW while Write Enable (WE ) and Chip Enable 2 (CE2)
is HIGH. The I/O pins are placed in a high-impedance st-
ate when the device is deselected: the outputs are disabled
during a write cycle.
The V62C1801024LL comes with a 1V data retention feature
and Lower Standby Power. The V62C1801024L is available in
a 32-pin 8 x 20 mm TSOP1 / STSOP / 48-fpBGA packages.
Logic Block Diagram
32-Pin TSOP1 / STSOP (See next page)
INPUT BUFFFEERR
A0
AAA211
AA32
AA43 11002244
AA54
AA65
10XX24
AA76 1024
A8
AA97
A8
COLUMN DECODER
COLUMN DECODER
A10 A11 A12 A13 A14 A15 A16
A9 A10 A11 A12 A13 A14 A15 A16
II//OO87
I/O1
I/O0
CONTROL
CCOIRNCTURIOTL
CIRCUIT
OE
WE
OCEE1
WCEE2
CE1
CE2
A11
A9
A8
A13
WE
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REV. 1.1 April 2001 V62C1801024L(L)
1
32 OE
31 A10
30 CE1
29 I/O8
28 I/O7
27 I/O6
26 I/O5
25 I/O4
24 GND
23 I/O3
22 I/O2
21 I/O1
20 A0
19 A1
18 A2
17 A3
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V62C1801024L(L)
Read Cycle (3,9) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter
Symbol -70
-85 -100
-150 Unit Note
Read Cycle Time
Min Max Min Max Min Max Min Max
tRC
70 - 85 - 100 - 150 -
ns
Address Access Time
tAA - 70 - 85 - 100 - 150 ns
Chip Enable Access Time
tACE - 70 - 85 - 100 - 150 ns
Output Enable Access Time
tOE - 40 - 40 - 50 - 70 ns
OutputHold from Address Change
tOH
10 - 10 - 10 - 10 -
ns
Chip Enable to Output in Low-Z
tCLZ 10 - 10 - 10 - 10 - ns 4,5
Chip Disable to Output in High-Z tCHZ - 30 - 35 - 40 - 50 ns 4,5
Output Enable to Output in Low-Z
tOLZ
5-5-5- 5 -
ns 4,5
Output Disable to Output in High-Z
tOHZ
- 25 - 30 - 35 - 40 ns 4,5
Power-Up Time
tPU 0 - 0 - 0 - 0 - ns 5
Power-Down Time
tPD
- 70 - 85 - 100 - 150 ns
5
Write Cycle (3,11) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter
Write Cycle Time
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
Write Pulse Width
Write Recovering Time
Data Valid to Write End
Data Hold Time
Write Enable to Output in High-Z
Output Active from Write End
Symbol -70
-85 -100 -150 Unit Note
Min Max Min Max Min Max Min Max
tWC 70 - 85 - 100 - 150 - ns
tCW 60 - 70 - 80 - 120 - ns
tAW
60 - 70 - 80 - 120 -
ns
tAS
0-0-0- 0 -
ns
tWP
50 - 60 - 70 - 100 -
ns
tWR
0-0-0- 0 -
ns
tDW 30 - 35 - 40 - 60 - ns
tDH
0-0-0- 0 -
ns
tWZ - 30 - 35 - 40 - 50 ns 4,5
tOW
5-5-5- 5 -
ns 4,5
REV. 1.1 April 2001 V62C1801024L(L)
5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for V62C1801024LL-70T electronic component. |
| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ V62C1801024LL-70T.PDF Datasheet ] | |
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