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PDF V58C3643204SAT Data sheet ( Hoja de datos )
| Número de pieza | V58C3643204SAT | |
| Descripción | HIGH PERFORMANCE 3.3 VOLT 2M X 32 DDR SDRAM 4 X 512K X 32 | |
| Fabricantes | Mosel Vitelic Corp | |
| Logotipo |  |
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MOSEL VITELIC
V58C3643204SAT
HIGH PERFORMANCE
3.3 VOLT 2M X 32 DDR SDRAM
4 X 512K X 32
PRELIMINARY
System Frequency (fCK)
Clock Cycle Time (tCK3)
Clock Cycle Time (tCK4)
45
225MHz
4.5 ns
50
200 MHz
5 ns
55
183 MHz
5.5 ns
60
166 MHz
6 ns
Features
s 4 banks x 512K x 32 organization
s High speed data transfer rates with system
frequency up to 225 MHz
s Data Mask for Write Control (DM)
s Four Banks controlled by BA0 & BA1
s Programmable CAS Latency: 3, 4
s Programmable Wrap Sequence: Sequential
or Interleave
s Programmable Burst Length:
2, 4, 8 full page for Sequential Type
2, 4, 8 full page for Interleave Type
s Automatic and Controlled Precharge Command
s Suspend Mode and Power Down Mode
s Auto Refresh and Self Refresh
s Refresh Interval: 2048 cycles/16ms
s Available in 100-pin TQFP
s SSTL-2 Compatible I/Os
s Double Data Rate (DDR)
s Bidirectional Data Strobe (DQs) for input and
output data, active on both edges
s On-Chip DLL aligns DQ and DQs transitions with
CLK transitions
s Differential clock inputs CLK and CLK
s Power Supply 3.3V ± 0.3V
Description
The V58C3643204SAT is a four bank DDR
DRAM organized as 4 banks x 512K x 32. The
V58C3643204SAT achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the
output data to a system clock
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are possible on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
100-pin TQFP
0°C to 70°C
•
CLK Cycle Time (ns)
-45 -50 -55 -60
••••
Power
Std. L
••
Temperature
Mark
Blank
V58C3643204SAT Rev. 1.4 August 2001
1
1 page  
MOSEL VITELIC
V58C3643204SAT
Auto Precharge Operation
The Auto Precharge operation can be issued by having column address A8 high when a Read or Write com-
mand is issued. If A10 is low when a Read or Write command is issued, then normal Read or Write burst op-
eration is executed and the bank remains active at the completion of the burst sequence. When the Auto
Precharge command is activated, the active bank automatically begins to precharge at the earliest possible
moment during the Read or Write cycle once tRAS(min) is satisfied.
Read with Auto Precharge
If a Read with Auto Precharge command is initiated, the DDR SDRAM will enter the precharge operation
N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency pro-
grammed into the device. Once the autoprecharge operation has begun, the bank cannot be reactivated until
the minimum precharge time (tRP) has been satisfied.
Read with Autoprecharge Timing
T0
CK, CK
Command
DQS
DQ
(CAS Latency = 2; Burst Length = 4)
T1 T2 T3 T4 T5 T6 T7 T8 T9
tRAS(min)
tRP(min)
BA
NOP R w/AP NOP
NOP
NOP
NOP
NOP
BA
D0 D1 D2 D3
Begin Autoprecharge
Earliest Bank A reactivate
V58C3643204SAT Rev. 1.4 August 2001
5
5 Page 
MOSEL VITELIC
Package Diagram
100-Pin TQFP
#100
#1
17.20 ± 0.20
14.00 ± 0.10
V58C3643204SAT
Dimensions in Millimeters
0 ~ 7∞
23.20 ± 0.20
20.00 ± 0.10
0.825
0.30 ± 0.08
0.13 MAX
0.65
1.00 ± 0.10
1.20 MAX *
0.10 MAX
0.05 MIN
0.80 ± 0.20
0.09~0.20
V58C3643204SAT Rev. 1.4 August 2001
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet V58C3643204SAT.PDF ] | |
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