V58C2256164S Datasheet PDF - Mosel Vitelic Corp
| Part Number | V58C2256164S | |
| Description | HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM | |
| Manufacturers | Mosel Vitelic Corp | |
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MOSEL VITELIC
V58C2256(804/404/164)S
HIGH PERFORMANCE
2.5 VOLT 256 Mbit DDR SDRAM
4 BANKS X 8Mbit X 8 (804)
4 BANKS X 4Mbit X 16 (164)
4 BANKS X 16Mbit X 4 (404)
Clock Cycle Time (tCK2)
Clock Cycle Time (tCK2.5)
System Frequency (fCK max)
6
DDR333B
7.5 ns
6 ns
166 MHz
7
DDR266A
7.5ns
7ns
143 MHz
PRELIMINARY
75
DDR266B
10 ns
7.5 ns
133 MHz
8
DDR200
10 ns
8 ns
125 MHz
Features
■ High speed data transfer rates with system
frequency up to 166 MHz
■ Data Mask for Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2, 2.5
■ Programmable Wrap Sequence: Sequential
or Interleave
■ Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■ Automatic and Controlled Precharge Command
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 8192 cycles/64 ms
■ Available in 66-pin 400 mil TSOP or 60 Ball SOC
BGA
■ SSTL-2 Compatible I/Os
■ Double Data Rate (DDR)
■ Bidirectional Data Strobe (DQS) for input and
output data, active on both edges
■ On-Chip DLL aligns DQ and DQs transitions with
CK transitions
■ Differential clock inputs CK and CK
■ Power Supply 2.5V ± 0.2V
■ QFC options for FET control. x4 parts.
*Note: DDR 333B Supports PC2700 module with 2.5-3-3 timing
DDR 266A Supports PC2100 module with 2-2-2 timing
DDR 266B Supports PC2100 module with 2.5-3-3 timing
DDR 200 Supports PC1600 module with 2-2-2 timing
Description
The V58C2256(804/404/164)S is a four bank
DDR DRAM organized as 4 banks x 8Mbit x 8 (804),
4 banks x 4Mbit x 16 (164), or 4 banks x 16Mbit x 4
(404). The V58C2256(804/404/164)S achieves high
speed data transfer rates by employing a chip archi-
tecture that prefetches multiple bits and then syn-
chronizes the output data to a system clock.
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are ocurring on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
JEDEC 66 TSOP II
60 SOC BGA
•
CK Cycle Time (ns)
-6 -7 -75 -8
• • ••
Power
Std.
•
L
•
Temperature
Mark
Blank
V58C2256(804/404/164)S Rev.1.4 October 2002
1
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MOSEL VITELIC
V58C2256(804/404/164)S
Block Diagram
32M x 8
Column Addresses
A0 - A9, AP, BA0, BA1
Row Addresses
A0 - A12, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Bank 0
8192 x 512
x 16 bit
Row decoder
Memory array
Bank 1
8192 x 512
x 16 bit
Row decoder
Memory array
Bank 2
8192 x 512
x 16bit
Row decoder
Memory array
Bank 3
8192 x 512
x 16bit
CK, CK
DQS
Input buffer Output buffer
DLL
Strobe
Gen.
DQ0-DQ7
Data Strobe
Control logic & timing generator
V58C2256(804/404/164)S Rev. 1.4 October 2002
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for V58C2256164S electronic component. |
| Information | Total 61 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ V58C2256164S.PDF Datasheet ] | |
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Featured Datasheets
| Part Number | Description | MFRS |
| V58C2256164S | The function is HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM. Mosel Vitelic Corp | |
| V58C2256164SC | The function is 256 Mbit DDR SDRAM. ProMOS Technologies |  |
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