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PDF V53C8128H Data sheet ( Hoja de datos )
| Número de pieza | V53C8128H | |
| Descripción | ULTRA-HIGH PERFORMANCE/ 128K X 8 BIT EDO PAGE MODE CMOS DYNAMIC RAM | |
| Fabricantes | Mosel Vitelic Corp | |
| Logotipo |  |
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MOSEL-VITELIC
V53C8128H
ULTRA-HIGH PERFORMANCE,
128K X 8 BIT EDO PAGE MODE
CMOS DYNAMIC RAM
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC)
Max. Column Address Access Time, (tCAA)
Min. Fast Page Mode With EDO Cycle Time, (tPC)
Min. Read/Write Cycle Time, (tRC)
35
35 ns
18 ns
14 ns
70 ns
40
40 ns
20 ns
15 ns
75 ns
PREVL5I3MCIN81A2R8YH
45
45 ns
22 ns
17 ns
80 ns
50
50 ns
24 ns
19 ns
90 ns
Features
s 128K x 8-bit organization
s RAS access time: 35, 40, 45, 50 ns
s EDO Page Mode supports sustained I/O data
rates up to 71.5 MHz
s Low power dissipation
• V53C8128H-50
— Operating Current – 135 mA max
— TTL Standby Current – 2.0 mA max
s Low CMOS Standby Current
• V53C8128H – 1.0 mA max
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
s Refresh Interval
• V53C8128H – 512 cycles/8 ms
s Available in 26/24 pin 300 mil SOJ package
Description
The V53C8128H is a high speed 131,072 x 8 bit
CMOS dynamic random access memory. The
V53C8128H offers a combination of features: EDO
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Page Mode
with extended data out operation allows random
access of up to 256 columns (x8) bits within a row
with cycle times as short as 14 ns. Because of static
circuitry, the CAS clock is not in the critical timing
path. The flow-through column address latches
allow address pipelining while relaxing many critical
system timing requirements for fast usable speed.
These features make the V53C8128H ideally suited
for graphics, digital signal processing and high
performance Peripherals.
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
Package Outline
K
•
Access Time (ns)
35 40 45
•••
50
•
V53C8128H Rev. 1.1 November 1997
1
Power
Std.
•
Temperature
Mark
Blank
1 page  
MOSEL-VITELIC
V53C8128H
AC Characteristics
TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
JEDEC
# Symbol Symbol Parameter
1 tRL1RH1 tRAS
2 tRL2RL2 tRC
3 tRH2RL2 tRP
4 tRL1CH1 tCSH
5 tCL1CH1 tCAS
6 tRL1CL1 tRCD
7 tWH2CL2 tRCS
8 tAVRL2
tASR
9 tRL1AX
tRAH
10 tAVCL2
tASC
11 tCL1AX
tCAH
12 tCL1RH1(R) tRSH (R)
13 tCH2RL2 tCRP
14 tCH2WX tRCH
RAS Pulse Width
Read or Write Cycle Time
RAS Precharge Time
CAS Hold Time
CAS Pulse Width
RAS to CAS Delay
Read Command Setup Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
RAS Hold Time (Read Cycle)
CAS to RAS Precharge Time
Read Command Hold Time
Referenced to CAS
15 tRH2WX tRRH
Read Command Hold Time
Referenced to RAS
16 tOEL1RH2 tROH
RAS Hold Time
Referenced to OE
17 tGL1QV
18 tCL1QV
19 tRL1QV
20 tAVQV
tOAC
tCAC
tRAC
tCAA
Access Time from OE
Access Time from CAS (EDO)
Access Time from RAS
Access Time from Column
Address
21 tCL1QX
22 tCH2QZ
23 tRL1AX
tLZ
tHZ
tAR
CAS to Low-Z Output
Output buffer turn-off delay time
Column Address Hold Time
from RAS
24 tRL1AV
tRAD
RAS to Column Address
Delay Time
25 tCL1RH1(W) tRSH (W)
RAS or CAS Hold Time
in Write Cycle
26 tWL1CH1 tCWL
Write Command to CAS
Lead Time
35 40 45 50
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
35 75K 40 75K 45 75K 50 75K ns
70 75 80 90
ns
25 25 25 30
ns
35 40 45 50
ns
7 8 9 9 ns
16 23 17 28 18 32 19 36 ns
0 0 0 0 ns 4
0 0 0 0 ns
6 7 8 9 ns
0 0 0 0 ns
4 5 6 7 ns
14 14 15 15
ns
5 5 5 5 ns
0 0 0 0 ns 5
0 0 0 0 ns 5
8 8 9 10 ns
12 12 13 14 ns
12 12 13 14 ns 6, 7
35 40 45 50 ns 6, 8, 9
18 20 22 24 ns 6, 7, 10
0000
06060708
28 30 35 40
ns
ns
ns
16
16
11 17 12 20 13 23 14 26 ns
11
12 12 13 14
ns
12 12 13 14
ns
V53C8128H Rev. 1.1 November 1997
5
5 Page 
MOSEL-VITELIC
V53C8128H
Waveforms of EDO Page Mode Read Cycle
RAS
V IH
V IL
CAS
V IH
V IL
t ASR (8)
t AR (23)
t RCD (6)
t CRP (13)
t PC (42)
t CP (43)
t CAS (5)
t RAH (9)
tASC (10)
t CSH (4)
tRAS (1)
t RP (3)
t RSH (R)(12)
tCAS (5)
t CRP (13)
t CAS (5)
tASC (10)
t CAH (11)
tCAR (44)
t CAH (11)
ADDRESS
V IH
V IL
ROW
ADDRESS
t RCS (7)
COLUMN
ADDRESS
COLUMN
ADDRESS
t RCH (14)
t CAH (11)
t RCS (7)
COLUMN
ADDRESS
t RCS (7)
t RCH (14)
V IH
WE
V IL
t CAA (20)
t OAC (17)
t CAP (45)
tCAA (20)
t OAC (17)
t RRH (15)
V IH
OE
V IL
t RAC (19)
t CAC (18)
t LZ (21)
t CAC (18)
t CAC (18)
V OH
I/O
V OL
t COH
VALID
DATA OUT
VALID
DATA OUT
t HZ (22)
VALID
DATA OUT
Waveforms of EDO Page Mode Write Cycle
t AR (23)
RAS
V IH
V IL
CAS
V IH
V IL
ADDRESS
V IH
V IL
t CRP (13)
t RCD (6)
t PC (42)
t CP (43)
t CAS (5)
t RAH (9)
t ASR (8)
t CSH (4)
t ASC (10)
t CAH (11)
ROW
ADD
t RAD (24)
t WCS (27)
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
t WCH (28)
V IH
WE
V IL
t WP (29)
t RAS (1)
t CAS (5)
t ASC (10)
t CAH (11)
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
t WCH (28)
t WP (29)
t LZ
t RP (3)
t RSH (W)(25)
t CAS (5)
t CAR (44)
t CAH (11)
COLUMN
ADDRESS
t CWL (26)
t RWL (31)
tWCH (28)
tWP (29)
t HZ (22)
t HZ (22)
t HZ (22)
2736 09
t CRP (13)
VIH
OE
VIL
V IH
I/O
V IL
t DS (32)
t DH (33)
t DS (32)
VALID
DATA IN
OPEN
t DH (33) t DS (32)
VALID
DATA IN
t DH (33)
VALID
DATA IN
OPEN
2736 10
V53C8128H Rev. 1.1 November 1997
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet V53C8128H.PDF ] | |
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