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PDF V53C16258L Data sheet ( Hoja de datos )
| Número de pieza | V53C16258L | |
| Descripción | HIGH PERFORMANCE 3.3 VOLT 256K X 16 EDO PAGE MODE CMOS DYNAMIC RAM OPTIONAL SELF REFRESH | |
| Fabricantes | Mosel Vitelic Corp | |
| Logotipo |  |
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MOSEL VITELIC
V53C16258L
HIGH PERFORMANCE
3.3 VOLT 256K X 16 EDO PAGE MODE
CMOS DYNAMIC RAM
OPTIONAL SELF REFRESH
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC)
Max. Column Address Access Time, (tCAA)
Min. Fast Page Mode Cycle Time, (tPC)
Min. Read/Write Cycle Time, (tRC)
35
35 ns
18 ns
14 ns
70 ns
40
40 ns
20 ns
15 ns
75 ns
45
45 ns
22 ns
17 ns
80 ns
50
50 ns
24 ns
19 ns
90 ns
Features
s 256K x 16-bit organization
s EDO Page Mode for a sustained data rate
of 71 MHz
s RAS access time: 35, 40, 45, 50 ns
s Dual CAS Inputs
s Low power dissipation
s Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, and Self Refresh
s Optional Self Refresh (V53C16258SL)
s Refresh Interval: Standard: 512 cycles/8ms
s Available in 40-pin 400 mil SOJ and
40/44L-pin 400 mil TSOP-II packages
s Single +3.3V ±0.3V Power Supply
s TTL Interface
Description
The V53C16258L is a 262,144 x 16 bit high-
performance CMOS dynamic random access
memory. The V53C16258L offers Page mode with
Extended Data Output. An address, CAS and RAS
input capacitances are reduced to one quarter
when the x4 DRAM is used to construct the same
memory density. The V53C16258L has symmetric
address and accepts 512 cycle 8ms interval.
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 512 x 16 bits,
within a page, with cycle times as short as 15ns.
The V53C16258L is ideally suited for a wide
variety of high performance portable computer
systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
KT
••
Access Time (ns)
35 40 45 50
••••
Power
Std.
•
V53C16258L Rev. 1.1 June 1999
1
Temperature
Mark
Blank
1 page  
MOSEL VITELIC
V53C16258L
AC Characteristics
TA = 0°C to 70°C, VCC = +3.3 V ±0.3V, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
# Symbol Parameter
1 tRAS
2 tRC
3 tRP
4 tCSH
5 tCAS
6 tRCD
7 tRCS
8 tASR
9 tRAH
10 tASC
11 tCAH
12 tRSH (R)
13 tCRP
14 tRCH
RAS Pulse Width
Read or Write Cycle Time
RAS Precharge Time
CAS Hold Time
CAS Pulse Width
RAS to CAS Delay
Read Command Setup Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
RAS Hold Time (Read Cycle)
CAS to RAS Precharge Time
Read Command Hold Time Referenced
to CAS
15 tRRH
Read Command Hold Time Referenced
to RAS
16 tROH
RAS Hold Time Referenced to OE
17 tOAC
Access Time from OE
18 tCAC
Access Time from CAS
19 tRAC
Access Time from RAS
20 tCAA
Access Time from Column Address
21 tLZ
OE or CAS to Low-Z Output
22 tHZ
OE or CAS to High-Z Output
23 tAR
Column Address Hold Time from RAS
24 tRAD
RAS to Column Address Delay Time
25 tRSH (W) RAS or CAS Hold Time in Write Cycle
26 tCWL
Write Command to CAS Lead Time
27 tWCS
Write Command Setup Time
28 tWCH
Write Command Hold Time
29 tWP
Write Pulse Width
30 tWCR
Write Command Hold Time from RAS
31 tRWL
Write Command to RAS Lead Time
32 tDS
Data in Setup Time
35 40 45 50
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
35 75 40 75 45 75K 50 75K ns
70 75 80 90 ns
25 25 25 30 ns
35 40 45 50 ns
6 7 8 9 ns
13 24 17 28 18 32 19 36 ns
0 0 0 0 ns 4
0 0 0 0 ns
6 7 8 9 ns
0 0 0 0 ns
5 5 5 6 7 ns
10 10 10 10 10 ns
5 5 5 5 ns
0 0 0 0 ns 5
0 0 0 0 ns 5
7 8 9 10 ns
11 12 13 14 ns 12
11 12 13 14 ns 6, 7, 14
35 40 45 50 ns 6, 8, 9
18 20 22 24 ns 6, 7, 10
0 0 0 0 ns 16
0 6 0 6 0 7 0 8 ns 16
25 30 35 40 ns
10 20 12 20 13 23 14 26 ns 11
10 10 10 10 ns
8 12 13 14 ns
0 0 0 0 ns 12, 13
5 5 6 7 ns
5 5 6 7 ns
25 30 35 40 ns
10 12 13 14 ns
0 0 0 0 ns 14
V53C16258L Rev. 1.1 June 1999
5
5 Page 
MOSEL VITELIC
V53C16258L
Waveforms of EDO Page Mode Read Cycle
RAS
V IH
V IL
UCAS, LCAS
V IH
V IL
ADDRESS
V IH
V IL
V IH
WE
V IL
V IH
OE
V IL
V OH
I/O
V OL
t AR (23)
t RCD (6)
t CRP (13)
tRAS (1)
t RP (3)
t PC (42)
t CP (43)
t CAS (5)
t RSH (R)(12)
tCAS (5)
t CRP (13)
t CAS (5)
t ASR (8)
t RAH (9)
tASC (10)
t CSH (4)
tASC (10)
t CAH (11)
ROW
ADDRESS
t RCS (7)
COLUMN
ADDRESS
COLUMN
ADDRESS
t RCH (14)
t CAH (11)
t RCS (7)
tCAR (44)
t CAH (11)
COLUMN
ADDRESS
t RCS (7)
t RCH (14)
t CAA (20)
t OAC (17)
t RAC (19)
t CAC (18)
t LZ (21)
t CAP (45)
t OES (52)
t CAC (18)
tCOH (5)
VALID
DATA OUT
tCAA (20)
t OAC (17)
t RRH (15)
tOEP (54)
t CAC (18)
VALID
DATA OUT
t HZ (22)
VALID
DATA OUT
t LZ
t HZ (22)
t HZ (22)
t HZ (22)
2736 09
Waveforms of EDO Page Mode Write Cycle
RAS
V IH
V IL
UCAS, LCAS
V IH
V IL
ADDRESS
V IH
V IL
WE V IH
V IL
t AR (23)
t RAS (1)
t CRP (13)
t RCD (6)
t PC (42)
t CP (43)
t CAS (5)
t CAS (5)
t RAH (9)
t ASR (8)
t CSH (4)
t ASC (10)
t CAH (11)
ROW
ADD
t RAD (24)
t WCS (27)
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
t WCH (28)
t WP (29)
t ASC (10)
t CAH (11)
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
t WCH (28)
t WP (29)
t RP (3)
t RSH (W)(25)
t CAS (5)
t CAR (44)
t CAH (11)
COLUMN
ADDRESS
t CWL (26)
t RWL (31)
tWCH (28)
tWP (29)
t CRP (13)
VIH
OE
VIL
V IH
I/O
V IL
V53C16258L Rev. 1.1 June 1999
t DS (32)
t DH (33)
t DS (32)
VALID
DATA IN
OPEN
t DH (33) t DS (32)
VALID
DATA IN
t DH (33)
VALID
DATA IN
Don’t Care
OPEN
2736 10
Undefined
11
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| PDF Descargar | [ Datasheet V53C16258L.PDF ] | |
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