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PDF V436632Y24V Data sheet ( Hoja de datos )
| Número de pieza | V436632Y24V | |
| Descripción | 256MB 144-PIN UNBUFFERED SDRAM SODIMM/ 32M X 64 3.3VOLT | |
| Fabricantes | Mosel Vitelic Corp | |
| Logotipo |  |
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MOSEL VITELIC
V436632Y24V
256MB 144-PIN UNBUFFERED SDRAM
SODIMM, 32M X 64 3.3VOLT
PRELIMINARY
Features
■ JEDEC-standard 144 pin, Small-Outline, Dual in
line Memory Module (SODIMM)
■ Serial Presence Detect with E2PROM
■ Nonbuffered
■ Fully Synchronous, All Signals Registered on
Positive Edge of System Clock
■ Single +3.3V (± 0.3V) Power Supply
■ All Device Pins are LVTTL Compatible
■ 8192 Refresh Cycles every 64 ms
■ Self-Refresh Mode
■ Internal Pipelined Operation; Column Address
can be changed every System Clock
■ Programmable Burst Lengths: 1, 2, 4, 8
■ Auto Precharge and Piecharge all Banks by A10
■ Data Mask Function by DQM
■ Mode Register Set Programming
■ Programmable (CAS Latency: 2, 3 Clocks)
■ TSOP component package
Description
The V436632Y24V memory module is organized
33,554,432 x 64 bits in a 144 pin SODIMM. The
32M x 64 memory module uses 8 Mosel-Vitelic 16M
x 16 SDRAM. The x64 modules are ideal for use in
high performance computer systems where
increased memory density and fast access times
are required.
Part Number
Speed
Grade
Configuration
V436632Y24VXTG-75PC -75PC, CL=2,3
(133 MHz)
32M x 64
V436632Y24VXTG-75
-75, CL=3
(133 MHz)
32M x 64
V436632Y24VXTG-10PC -10PC, CL=2,3
(100 MHz)
32M x 64
32M x 8
32M x 8
32M x 8
32M x 8
1 59 61
Pin 2 on Backside
143
Pin 144 on Backside
V436632Y24V Rev.1.2 March 2002
1
1 page  
MOSEL VITELIC
SPD-Table for modules: (Continued)
Byte
Number
29
30
31
64
33
34
35
62-61
62
63
64
65-71
72
73-90
91-92
93
94
95-98
99-125
126
127
128+
Function Described
SPD Entry Value
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (Per Bank)
15 ns/20 ns
42 ns/45 ns
128 Mbyte
SDRAM Input Setup Time
1.5 ns/2.0 ns
SDRAM Input Hold Time
0.8 ns/ 1.0 ns
SDRAM Data Input Setup Time
1.5 ns/2.0 ns
SDRAM Data Input Hold Time
0.8 ns/1.0 ns
Superset Information (May be used in Future)
SPD Revision
Revision 2 / 1.2
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Mosel Vitelic
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
1 = US, 2 = Taiwan
Module Part Number (ASCII)
V436632Y24V
PCB Identification Code
Current PCB Revision
Assembly Manufacturing Date (Year)
Binary Coded year (BCD)
Assembly Manufacturing Date (Week)
Binary Coded week (BCD)
Assembly Serial Number
byte 95 = LSB, byte 98 =
MSB
Reserved
Intel Specification for Frequency
Supported Frequency
Unused Storage Location
-75PC
0F
2A
20
15
08
15
08
00
02
E5
40
00
00
64
00
V436632Y24V
Hex Value
-75
14
2D
20
15
08
15
08
00
02
2A
40
00
-10PC
14
2D
20
20
10
20
10
00
12
98
40
00
00 00
64 64
00 00
V436632Y24V Rev. 1.2 March 2002
5
5 Page 
MOSEL VITELIC
Module Label Information
V436632Y24V
Label Information
Part Number
Criteria of PC100 or PC133
(refer to MVI datasheet)
DIMM manufacture date code
Module Density
MOSEL VITELIC
VV4443336666361266Y4R2S42V24X4XTVXGAX--TXXXGX-11025P2815CM62MBMBBCLCCXLLXX
PC133U-XXX-542-A
00113300--MK668822116655
Assembly in Taiwan
CAS Latency
2 = CL2
3 = CL3
PC133 U - XXX - 54 2 - A
UNBUFFERED DIMM
CL = 3 or 2 (CLK)
tRCD = 3 or 2 (CLK)
tRP = 3 or 2 (CLK)
Gerber file Intel® PC100 x 18166BBasaesded
JEDEC SPD Revision 2
tAC = 5.4 ns
V436632Y24V Rev. 1.2 March 2002
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet V436632Y24V.PDF ] | |
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