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PDF V320 Data sheet ( Hoja de datos )
| Número de pieza | V320 | |
| Descripción | V320 8-Bit Registered Bus Transceiver | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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April 1998
Revised October 1998
V320
8-Bit Registered Bus Transceiver
General Description
The V320 is an 8-bit universal bus transceiver designed for
high speed interfacing with the VME320 backplane. It has
output characteristics optimized for driving large capacitive
loads and features modified input levels (VIH/VIL) for
increased noise immunity and reduced input skew. The
V320 functionality consists of bus transceiver circuits with
3-STATE, D-type flip-flops, and control circuitry arranged
for multiplexed transmission of data directly from the input
bus or from the internal registers. Data on the A or B bus
will be clocked into the registers as the appropriate clock
pin goes to a high logic level. OE and direction pins are
provided to control the transceiver function. In the trans-
ceiver mode, data present at the high impedance port may
be stored in either the A or B register or in both. The select
controls can multiplex stored and real time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control OE is active
LOW. In the isolation mode (OE HIGH) A data may be
stored in the B register and/or B data may be stored in the
A register.
Features
s Independent registers for A and B buses
s Multiplexed real-time and stored data
s Guaranteed output skew
s Guaranteed MOS (Multiple Output Switching) Specifica-
tions
s Output switching specified for both 50 pF and 250 pF,
and 500 pF loads
s Guaranteed simultaneous switching noise level (VOLP/
VOLV) and dynamic threshold performance (VIHD/VILD)
s Glitch free power up/down high impedance for live inser-
tion
s BiCMOS technology for high drive and low power dissi-
pation
s −40°C to 85°C commercial temperature and VCC specifi-
cations
s Modified specifications across VCC and temperature
(VCC = 5.0V ±1%, T = 25°C ± 20°C) present more realis-
tic system conditions
s Available in TSSOP (MTC)
Ordering Code:
Order Number Package Number
Package Description
V320MTC
MTC24
24-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
D Direction A-to-B (High) B-to A (Low)
OE Output Enable (Active LOW)
CLKAB/SELAB A-to-B Clock/Select
CLKBA/SELBA B-to-A Clock/Select
A0–7
A Inputs/Outputs (TTL)
B0–7
B Inputs/Outputs (TTL)
© 1998 Fairchild Semiconductor Corporation DS500149.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
(−40°C to 85°C, VCC = 4.5V to 5.5V) 1 Output Switching
Symbol
From
(Input)
Mode
To
(Output)
Min Typ Max Units
Output Load: CL = 50 pF, RL= 500Ω, 1 Output Switching
tPLH, tPHL CLKAB/CLKBA
Register
Bus A or B
1.7
5.6 ns
tPLH, tPHL Bus A or B
Transparent
Bus A or B
1.5
4.8 ns
tPLH, tPHL SELAB/SELBA
Select Bus
Bus A or B
1.5
5.9 ns
tPLZ, tPHZ OE
Output Disable
Bus A or B
1.5
6.0 ns
tPZH, tPZL OE
Output Enable
Bus A or B
1.5
6.3 ns
tPLZ, tPHZ Direction (D)
Dir. Disable
Bus A or B
1.5
6.0 ns
tPZH, tPZL Direction (D)
Dir. Enable
Bus A or B
1.5
6.3 ns
tRISE
Transition Time, Outputs (1V to 2V)
0.3 1.2 ns
tFALL
Transition Time, Outputs (1V to 2V)
0.3 1.4 ns
Output Load: CL = 250 pF, RL = 500Ω, 1 Output Switching
tPLH, tPHL CLKAB/CLKBA
Register
Bus A or B
2.0
7.5 ns
tPLH, tPHL Bus A or B
Transparent
Bus A or B
2.0
7.0 ns
tPLH, tPHL SELAB/SELBA
Select Bus
Bus A or B
2.0
7.5 ns
tPLZ, tPHZ OE
Output Disable
Bus A or B
(Note 5)
(Note 5)
ns
tPZH, tPZL OE
Output Enable
Bus A or B
2.0
8.0 ns
tPLZ, tPHZ Direction (D)
Dir. Disable
Bus A or B
(Note 5)
(Note 5)
ns
tPZH, tPZL Direction (D)
Dir. Enable
Bus A or B
2.0
8.3 ns
tRISE
Transition Time, Outputs (1V to 2V)
1.7 3.9 ns
tFALL
Transition Time, Outputs (1V to 2V)
0.8 3.1 ns
Output Load: CL = 500 pF, RL = 500Ω, Output Switching
tPLHtPHL CLKAB/CLKBA
Register
Bus A or B
3.0
12.2 ns
tPLHtPHL Bus A or B
Transparent
Bus A or B
3.0
11.6 ns
tPLHtPHL SELAB/SELBA
Select Bus
Bus A or B
3.0
12.4 ns
tPLZ, tPHZ OE
Output Disable
Bus A or B
(Note 5)
(Note 5)
ns
tPZH, tPZL OE
Output Enable
Bus A or B
3.0
12.6 ns
tPLZ, tPHZ Direction (D)
Dir. Disable
Bus A or B
(Note 5)
(Note 5)
ns
tPZH, tPZL Direction (D)
Dir. Enable
Bus A or B
6.3
13.2 ns
tRISE
Transition Time, Outputs (1V to 2V)
3.5 7.2 ns
tFALL
Transition Time, Outputs (1V to 2V)
1.4 5.1 ns
Note 5: 3-STATE delays are dominated by the RC Network (500 Ω/ 250 pF, or 500 Ω/ 500 pF) on the output and thus have been excluded from this
datasheet.
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet V320.PDF ] | |
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