PDF VSP3010Y Data sheet ( Hoja de datos )

Número de pieza	VSP3010Y
Descripción	12-Bit/ 12MHz CCD/CIS SIGNAL PROCESSOR
Fabricantes	Burr-Brown Corporation
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No Preview Available ! ® VSP3010 VSP3010 For most current data sheet and other product information, visit www.burr-brown.com TM 12-Bit, 12MHz CCD/CIS SIGNAL PROCESSOR FEATURES q 12-BIT, 12MHz A/D CONVERTER q GUARANTEED NO MISSING CODES q 3-CHANNEL, 4MHz COLOR SCAN MODE: Correlated Double Samplers 8-Bit Offset Adjustment DACs 0dB to +13dB PGAs q A/D INPUT MONITOR q INTERNAL VOLTAGE REFERENCE q SINGLE +5V SUPPLY q 3V OR 5V DIGITAL OUTPUT q LOW POWER: 500mW typ (CCD Mode) APPLICATIONS q CCD AND CIS COLOR SCANNERS q FAX AND MULTI-FUNCTION MACHINES q INDUSTRIAL /MEDICAL IMAGING SYSTEMS DESCRIPTION The VSP3010 is a complete, three-channel image signal processor for Charge Coupled Device (CCD) or Contact Image Sensor (CIS) systems. Each chan- nel contains sensor signal sampling, Black Level adjustment and a programmable gain amplifier. The three inputs are multiplexed into a high speed, 12-bit analog-to-digital converter. Input circuitry can be configured, by digital command, for CCD or CIS sensors. A Black Clamp and Correlated Double Samplers (CDS) are provided for CCD sensors. For CIS devices, the VSP3010 provides a single-ended sampler and a reference input. The VSP3010 is available in a 48-lead LQFP package and operates from 0°C to +85°C with a single +5V supply. CLP CK1 CK2 STRT ADCCK TP0 VREF RINP RINN Clamp GINP GINN Clamp BINP BINN Clamp Offset Register R G B 8 8-Bit DAC 8 8-Bit DAC 8 8-Bit DAC 8 CDS PGA 5 Timing M1 M2 M3 Bandgap Reference CDS PGA 5 MUX CDS PGA 5 VSP3010 Configuration Register Gain Adjust Register R G B 5 8 12-Bit A/D 12 Register Port 3 8 CM REFT REFB VDRV B0-B11 (D0-D7, A0-A2) OE P/S WRT RD SCLK SD International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ©1999 Burr-Brown Corporation PDS-1542A Printed in U.S.A. June, 1999 1 page TIMING DIAGRAMS Timing specifications = tMIN to tMAX with +5V power supply. Timing for 3-Channel CCD/CIS Mode 3-Channel CCD Mode CCD STRT CK1 CK2 ADCCK tST R R1, G1, B1 tS tS tCK1AP tSET tCK12A tCCK tCCK G tCKP tCK2A tCK21A tADCCK2 tCNV B R1 tCK1A G1 3-Channel CIS Mode CIS STRT CK1 tST ADCCK R R1, G1, B1 tS tSET tCK1A tCCK tCCK G tCKP tADCCK1 tCNV B R1 tCK1AP G1 B1 B1 SYMBOL tCK1AP tCK1A tCK2A tCCK tCKP tS tCK12A tCK21A tSET tADCCK2 tADCCK1 tCNV tST PARAMETER 3-Channel Conversion Rate CK1 Pulse Width CK2 Pulse Width ADCCK Pulse Width ADCCK Period Sampling Delay CK1 Falling Edge to CK2 Rising Edge CK2 Falling Edge to CK1 Rising Edge ADCCK Falling Edge to CK1 Rising Edge ADCCK Falling Edge to CK2 Falling Edge ADCCK Falling Edge to CK1 Falling Edge Conversion Delay Start Conversion Time MIN 200 15 15 35 83 10 15 50 10 20 20 22 20 TYP 250 70 70 42 MAX 100 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ® 5 VSP3010 5 Page In this mode, the CDS becomes a CIS signal processing circuit (acting like a track-and-hold). Each CIS signal pro- cessing circuit consists of a 5-bit PGA (0dB to +13dB) and an 8-bit offset DAC (+50mV to –150mV). A 3-to-1 analog MUX follows the CIS signal processing circuits and feeds a high performance 12-bit A/D converter. The analog MUX is not cycling between channels in this mode. Instead, the analog MUX is connected to a specific channel, depending on the data in the Configuration Register. As specified in the “1-Channel CIS Mode” timing diagram, the active period of CK1 (tCK1B) must be in the LOW period of ADCCK. If it is in the HIGH period of ADCCK, the VSP3010 will not function properly. ANALOG PGA There is one analog PGA on each channel. Each analog PGA is controlled by a 5-bit PGA gain register. The analog PGA gain varies from 1 to 4.44 (0dB to +13dB). The transfer function of the PGA is: Gain = 4/(4 – 0.1 • X) where X is the integer representation of the 5-bit PGA gain register. Figure 1 shows the PGA transfer function plot. 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 PGA TRANSFER FUNCTION 5 10 15 20 25 PGA Gain Setting 14 12 10 8 6 4 2 0 0 PGA TRANSFER FUNCTION 5 10 15 20 25 PGA Gain Setting FIGURE 1. PGA Transfer Function Plot. 31 31 CHOOSING AC INPUT COUPLING CAPACITORS The purpose of the input coupling capacitor is to isolate the DC output of the CCD array from affecting the VSP3010. The internal clamping circuitry restores the necessary DC component to the CCD output signal. The internal clamp voltage, VCLAMP, is derived from the reference. VCLAMP depends on the value of VREF; if VREF is set to 1V, VCLAMP is 2.5V and if VREF is set to 1.5V, VCLAMP is 3V. There are many factors that determine the size of the input coupling capacitors including CCD signal swing, voltage droop across the input capacitor since the last clamp interval, leakage current of the VSP3010 input circuitry, and the time period of CK1. Figure 2 shows a simplified equivalent circuit of the VSP3010 inputs. In this equivalent circuit, the input cou- pling capacitor, CIN, and the sampling capacitor, C1, are constructed as a capacitor divider (during CK1). For AC analysis, op amp inputs are grounded. Therefore, the sam- pling voltage, VS (during CK1) is: VS = (CIN/CIN + C1)) • VIN From this equation, we see that a larger value of CIN makes VS closer to VIN. In other words, the input signal VIN will be attenuated less if CIN is large. However, there is a disadvan- tage to using a large value of CIN: the larger the CIN, the more dummy or optical black pixels must be used to restore the DC component of the input signal. CIN VS VIN CLP CK1 CK1 C1 4pF C2 4pF CK2 OP AMP VCLAMP FIGURE 2. Equivalent Circuit of VSP3010 Inputs. CHOOSING CMAX AND CMIN As mentioned previously, a large CIN is preferable if there is enough time for the CLP signal to charge up CIN. Typically, 0.01µF to 0.1µF of CIN can be used for most cases. In order to optimize CIN, the following two equations can be used to calculate CMAX and CMIN: CMAX = ( tCK1 • N)/[RSW • ln (VD/VERROR)] where, tCK1 is the time when both CK1 and CLP are HIGH and N is the number of black pixels, RSW is the total switch ® 11 VSP3010 11 Page

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