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X76F128LE-2.7 fiches techniques PDF

Xicor - Secure SerialFlash

Numéro de référence X76F128LE-2.7
Description Secure SerialFlash
Fabricant Xicor 
Logo Xicor 





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X76F128LE-2.7 fiche technique
128K
X76F128
16Kx8+64x8
Secure SerialFlash
FEATURES
• 64-bit Password Security
—Five 64-bit Passwords for Read, Program
and Reset
• 16384 Byte+64 Byte Password Protected Arrays
—Seperate Read Passwords
—Seperate Write Passwords
—Reset Password
• Programmable Passwords
• Retry Counter Register
—Allows 8 tries before clearing of both arrays
—Password Protected Reset
• 32-bit Response to Reset (RST Input)
• 64 byte Sector Program
• 400kHz Clock Rate
• 2 wire Serial Interface
• Low Power CMOS
—2.7 to 5.5V operation
—Standby current Less than 1µA
—Active current less than 3 mA
• High Reliability Endurance:
—100,000 Write Cycles
• Data Retention: 100 years
• Available in:
—SmartCard Module
—TQFP Package
DESCRIPTION
The X76F128 is a Password Access Security Supervisor,
containing one 131072-bit Secure SerialFlash array and
one 512-bit Secure SerialFlash array. Access to each
memory array is controlled by two 64-bit passwords.
These passwords protect read and write operations of
the memory array. A separate RESET password is used
to reset the passwords and clear the memory arrays in
the event the read and write passwords are lost.
The X76F128 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA). Access to the device
is controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X76F128 also features a synchronous response to
reset providing an automatic output of a hard-wired 32-bit
data stream conforming to the industry standard for
memory cards.
The X76F128 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
Functional Diagram
CS
SCL
SDA
INTERFACE
LOGIC
RST
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7052 10/7/97 T0/C0/D0 SH
CHIP ENABLE
DATA TRANSFER
ARRAY ACCESS
ENABLE
PASSWORD ARRAY
AND PASSWORD
VERIFICATION LOGIC
RESET
RESPONSE REGISTER
1
16K BYTE
SerialFlash ARRAY
ARRAY 0
(PASSWORD PROTECTED)
64 BYTE
SerialFlash ARRAY
ARRAY 1
(PASSWORD PROTECTED)
RETRY COUNTER
7052 FM 01
Characteristics subject to change without notice

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