X28C256PM-35 Datasheet PDF - Xicor
| Part Number | X28C256PM-35 | |
| Description | 5 Volt/ Byte Alterable E2PROM | |
| Manufacturers | Xicor | |
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X28C256
256K
X28C256
5 Volt, Byte Alterable E2PROM
32K x 8 Bit
FEATURES
• Access Time: 200ns
• Simple Byte and Page Write
— Single 5V Supply
—No External High Voltages or VPP Control
Circuits
— Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• Low Power CMOS:
—Active: 60mA
—Standby: 200µA
• Software Data Protection
— Protects Data Against System Level
Inadvertent Writes
• High Speed Page Write Capability
• Highly Reliable Direct Write™ Cell
— Endurance: 100,000 Write Cycles
— Data Retention: 100 Years
• Early End of Write Detection
— DATA Polling
—Toggle Bit Polling
PIN CONFIGURATION
DESCRIPTION
The X28C256 is an 32K x 8 E2PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C256 is a 5V only device. The
X28C256 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard RAMs.
The X28C256 supports a 64-byte page write operation,
effectively providing a 78µs/byte write cycle and en-
abling the entire memory to be typically written in less
than 2.5 seconds. The X28C256 also features DATA
and Toggle Bit Polling, a system software support
scheme used to indicate the early completion of a write
cycle. In addition, the X28C256 includes a user-optional
software data protection mode that further enhances
Xicor’s hardware write protect capability.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
LCC
PLCC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
X28C256
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
3855 FHD F02
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 A11
A3 8
A2 9
X28C256
26 NC
25 OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0
13 21
14 15 16 17 18 19 20
I/O6
3855 FHD F03
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP
X28C256
32 A3
31 A4
30 A5
29 A6
28 A7
27 A12
26 A14
25 NC
24 VCC
23 NC
22 WE
21 A13
20 A8
19 A9
18 A11
17 OE
3855 ILL F23
© Xicor, Inc. 1991, 1995 Patents Pending
3855-1.9 8/1/97 T1/C0/D8 EW
1 Characteristics subject to change without notice
|
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X28C256
THE TOGGLE BIT I/O6
Figure 4. Toggle Bit Bus Sequence
LAST
WE WRITE
CE
OE
I/O6
VOH
*
VOL
* Beginning and ending state of I/O6 will vary.
Figure 5. Toggle Bit Software Flow
LAST WRITE
LOAD ACCUM
FROM ADDR n
HIGH Z
*
X28C256
READY
3855 FHD F14
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28C256 memories that is frequently updated.
The timing diagram in Figure 4 illustrates the sequence
of events on the bus. The software flow diagram in
Figure 5 illustrates a method for polling the Toggle Bit.
COMPARE
ACCUM WITH
ADDR n
COMPARE
OK?
YES
X28C256
READY
NO
3855 FHD F15
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for X28C256PM-35 electronic component. |
| Information | Total 24 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ X28C256PM-35.PDF Datasheet ] | |
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