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Xicor - V CC Supervisory Circuit w/Serial E 2 PROM

Numéro de référence X25168S14
Description V CC Supervisory Circuit w/Serial E 2 PROM
Fabricant Xicor 
Logo Xicor 





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X25168S14 fiche technique
64K
X25648/49,
8K x 8 Bit
32K
X25328/29,
4K x 8 Bit
16K
X25168/69
2K x 8 Bit
VCC Supervisory Circuit w/Serial E2PROM
FEATURES
DESCRIPTION
• Low Vcc Detection and Reset Assertion
—Reset Signal Valid to Vcc=1V
• Save Critical Data With Block LockTM Protection
—Block LockTM Protect 0, 1/4, 1/2 or all of
Serial E2PROM Memory Array
• In Circuit Programmable ROM Mode
• Long Battery Life With Low Power Consumption
—<1µA Max Standby Current
—<5mA Max Active Current during Write
—<400µA Max Active Current during Read
• 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power
Supply Operation
• 2MHz Clock Rate
• Minimize Programming Time
—32 Byte Page Write Mode
—Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• SPI Modes (0,0 & 1,1)
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
• High Reliability
• Available Packages
—14-Lead SOIC (X2564X)
—14-Lead TSSOP (X2532X, X2516X)
—8-Lead SOIC (X2532X, X2516X)
These devices combines two popular functions, Supply
Voltage Supervision and Serial E2PROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
The user’s system is protected from low voltage condi-
tions by the devices low Vcc detection circuitry. When
Vcc falls below the minimum Vcc trip point, the system is
reset. RESET/RESET is asserted until Vcc returns to
proper operating levels and stabilizes.
The memory portion of the device is a CMOS Serial
E2PROM array with Xicor’s Block LockTM Protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct WriteTM cell,
providing a minimum endurance of 100,000 cycles per
sector and a minimum data retention of 100 years.
BLOCK DIAGRAM
SI
SO
SCK
CS
RESET/RESET
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
RESET
CONTROL
X - DECODE
LOGIC
STATUS
REGISTER
PAGE DECODE LOGIC
32 8
SERIAL
E2PROM
ARRAY
VCC
LOW
VOLTAGE
SENSE
PROGRAMMING,
WP BLOCK LOCK &
ICP ROM CONTROL
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7032 -1.1 6/17/97 T1/C0/D0 SH
1
HIGH
VOLTAGE
CONTROL
7036 FRM 01
Characteristics subject to change without notice

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