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Número de pieza | X25165S14 | |
Descripción | Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM | |
Fabricantes | Xicor | |
Logotipo | ![]() |
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Hay una vista previa y un enlace de descarga de X25165S14 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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64K
X25643/45
8K x 8 Bit
32K
X25323/25
4K x 8 Bit
16K
X25163/65
2K x 8 Bit
Programmable Watchdog Timer & VCC Supervisory Circuit w/Serial E2PROM
FEATURES
DESCRIPTION
• Programmable Watchdog Timer
• Low Vcc Detection and Reset Assertion
—Reset Signal Valid to Vcc=1V
• Save Critical Data With Block LockTM Protection
—Block LockTM Protect 0, 1/4, 1/2 or all of
Serial E2PROM Memory Array
• In Circuit Programmable ROM Mode
• Long Battery Life With Low Power Consumption
—<50µA Max Standby Current, Watchdog On
—<1µA Max Standby Current, Watchdog Off
—<5mA Max Active Current during Write
—<400µA Max Active Current during Read
• 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power
Supply Operation
• 2MHz Clock Rate
• Minimize Programming Time
—32 Byte Page Write Mode
—Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• SPI Modes (0,0 & 1,1)
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
• High Reliability
• Available Packages
—14-Lead SOIC (X2564x)
—14-Lead TSSOP (X2532x, X2516x)
—8-Lead SOIC (X2532x, X2516x)
These devices combine three popular functions, Watch-
dog Timer, Supply Voltage Supervision, and Serial
E2PROM Memory in one package. This combination low-
ers system cost, reduces board space requirements, and
increases reliability.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. During a system failure,
the device will respond with a RESET/RESET signal
after a selectable time-out interval. The user selects the
interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The user’s system is protected from low voltage condi-
tions by the device’s low Vcc detection circuitry. When
Vcc falls below the minimum Vcc trip point, the system is
reset. RESET/RESET is asserted until Vcc returns to
proper operating levels and stabilizes.
The memory portion of the device is a CMOS Serial
E2PROM array with Xicor’s Block LockTM Protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct WriteTM cell,
providing a minimum endurance of 100,000 cycles per
sector and a minimum data retention of 100 years.
BLOCK DIAGRAM
SI
SO
SCK
CS
RESET/RESET
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
RESET
CONTROL
X - DECODE
LOGIC
STATUS
REGISTER
PAGE DECODE LOGIC
32 8
SERIAL
E2PROM
ARRAY
VCC
LOW
VOLTAGE
SENSE
WATCHDOG
TIMER
WP
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7049 -1.0 6/20/97 T0/C0/D0 SH
PROGRAMMING,
BLOCK LOCK &
ICP ROM CONTROL
1
HIGH
VOLTAGE
CONTROL
7036 FRM 01
Characteristics subject to change without notice
1 page ![]() ![]() X25643/45
X25323/25
X25163/65
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of the
last data byte to be written is clocked in. If it is brought
HIGH at any other time, the write operation will not be
completed (Figure 4).
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits 0
and 1 must be “0” .
While the write is in progress following a Status Register
or E2PROM Sequence, the Status Register may be read
to check the WIP bit. During this time the WIP bit will be
high.
RESET/RESET Operation
The RESET (X25xx3) output is designed to go LOW
whenever VCC has dropped below the minimum trip point
and/or the Watchdog timer has reached its programmable
time-out limit.
The RESET (X25xx5) output is designed to go HIGH
whenever VCC has dropped below the minimum trip point
and/or the watchdog timer has reached its programmable
time-out limit.
The RESET/RESET output is an open drain output and
requires a pull up resistor.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The Write Enable Latch is reset.
• The Flag Bit is reset.
• Reset Signal is active for tPURST.
Data Protection
The following circuitry has been included to prevent inad-
vertent writes:
• A WREN instruction must be issued to set the Write
Enable Latch.
• CS must come HIGH at the proper clock count in order
to start a nonvolatile write cycle.
Figure 1. Read E2PROM Array Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30
INSTRUCTION
SI
HIGH IMPEDANCE
SO
16 BIT ADDRESS
15 14 13
3210
DATA OUT
7 654321 0
MSB
7036 FRM 03
5
5 Page ![]() ![]() X25643/45
X25323/25
X25163/65
Serial Output Timing
CS
SCK
SO
t CYC
tV
MSB OUT
MSB–1 OUT
tHO
tWH
t WL
t LAG
LSB OUT
tDIS
SI
ADDR
LSB IN
Serial Input Timing
CS
SCK
SI
tLEAD
tSU t H
MSB IN
HIGH IMPEDANCE
SO
tCS
tLAG
tRI t FI
LSB IN
11
11 Page |
Páginas | Total 16 Páginas | |
PDF Descargar | [ Datasheet X25165S14.PDF ] |
Número de pieza | Descripción | Fabricantes |
X25165S14 | Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM | ![]() Xicor |
X25165S14-1.8 | Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM | ![]() Xicor |
X25165S14-2.7 | Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM | ![]() Xicor |
X25165S14I | Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM | ![]() Xicor |
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