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X25057VI-1.8 fiches techniques PDF

Xicor - 5MHz Low Power SPI Serial E 2 PROM with IDLock Memory

Numéro de référence X25057VI-1.8
Description 5MHz Low Power SPI Serial E 2 PROM with IDLock Memory
Fabricant Xicor 
Logo Xicor 





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X25057VI-1.8 fiche technique
4K
X25057
512 x 8 Bit
5MHz Low Power SPI Serial E2PROM with IDLock™ Memory
FEATURES
• 5MHz Clock Rate
• IDLock™ Memory
—IDLock First or Last Page, Any 1/4 or Lower 1/2
of E2PROM Array
• Low Power CMOS
—<1µA Standby Current
—<3mA Active Current during Write
—<400µA Active Current during Read
• 1.8V to 3.6V, 2.7V-5.5V or 4.5V to 5.5V Operation
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
• SPI Modes (0,0 & 1,1)
• 512 x 8 Bits
—16 Byte Page Mode
• Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• High Reliability
—Endurance: 100,000 Cycles/Byte
—Data Retention: 100 Years
—ESD: 2000V on all pins
• 8-Lead MSOP Package
• 8-Lead TSSOP Package
• 8-Lead SOIC Package
• 8-Lead PDIP Package
DESCRIPTION
The X25057 is a CMOS 4K-bit serial E2PROM, internally
organized as 512 x 8. The X25057 features a Serial
Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
IDLock is a programmable locking mechanism which
allows the user to lock system ID and parametric data in
different portions of the E2PROM memory space,
ranging from as little as one page to as much as 1/2 of
the total array. The X25057 also features a WP pin that
can be used for hardwire protection of the part, disabling
all write attempts, as well as a Write Enable Latch that
must be set before a write operation can be initiated.
The X25057 utilizes Xicor’s proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
SI
SO
SCK
CS
COMMAND
DECODE
AND
CONTROL
LOGIC
X
DECODE
LOGIC
DATA REGISTER
Y DECODE LOGIC
16 8
32
4K E2PROM
ARRAY
(512 x 8)
WP WRITE CONTROL LOGIC
©Xicor, Inc. 1994 – 1997 Patents Pending
7033-1.1 5/8/97 T1/C0/D0 SH
1
HIGH VOLTAGE
CONTROL
7033 FRM F01
Characteristics subject to change without notice

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