X25040PM Datasheet PDF - Xicor
| Part Number | X25040PM | |
| Description | SPI Serial E2PROM with Block LockTM Protection | |
| Manufacturers | Xicor | |
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APPLICATION NOTES
AVA I L A B L E
X25040AN9 • AN18 • AN31 • AN37 • AN40
4K
X25040
512 x 8 Bit
SPI Serial E2PROM with Block LockTM Protection
FEATURES
• 1MHz Clock Rate
• SPI Modes (0,0 & 1,1)
• 512 X 8 Bits
—4 Byte Page Mode
• Low Power CMOS
—150µA Standby Current
—3mA Active Current
• 2.7V To 5.5V Power Supply
• Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM Array
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Latch
—Write Protect Pin
• Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
• 8-Lead PDlP Package
• 8-Lead SOIC Package
DESCRIPTION
The X25040 is a CMOS 4096-bit serial E2PROM, inter-
nally organized as 512 x 8. The X25040 features a Serial
Peripheral Interface (SPI) and software protocol allow-
ing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is con-
trolled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The X25040 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25040 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25040 disabling all write attempts, thus providing
a mechanism for limiting end user capability of altering
the memory.
The X25040 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
STATUS
REGISTER
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
32
32
64
512 BYTE
ARRAY
32 X 32
32 X 32
64 X 32
WRITE
CONTROL
AND
WP TIMING
LOGIC
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
6451-3.6 6/10/96 T5/C1/D0 NS
1
48
Y DECODE
DATA REGISTER
6451 FHD F01
Characteristics subject to change without notice
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X25040
Operational Notes
The X25040 powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
• CS must come HIGH at the proper clock count in
order to start a write cycle.
Figure 1. Read E2PROM Array Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
INSTRUCTION
BYTE ADDRESS
SI 8 7 6 5 4 3 2 1 0
9TH BIT OF ADDRESS
HIGH IMPEDANCE
SO
DATA OUT
76543210
MSB
6451 FHD F14
Figure 2. Read Status Register Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
INSTRUCTION
SI
HIGH IMPEDANCE
SO
76
MSB
DATA OUT
5432
10
6451 ILL F13
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for X25040PM electronic component. |
| Information | Total 14 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ X25040PM.PDF Datasheet ] | |
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