X24C01M-3.5 Datasheet PDF - Xicor
| Part Number | X24C01M-3.5 | |
| Description | Serial E2PROM | |
| Manufacturers | Xicor | |
| Logo |  |
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There is a preview and X24C01M-3.5 download ( pdf file ) link at the bottom of this page. Total 14 Pages | ||
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XPr2e4liCm0in1ary Information
1K
X24C01
Serial E2PROM
128 x 8 Bit
FEATURES
• 2.7V to 5.5V Power Supply
• Low Power CMOS
—Active Current Less Than 1 mA
—Standby Current Less Than 50 µA
• Internally Organized 128 x 8
• 2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
• Four Byte Page Write Mode
• Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
• 8-Pin Mini-DIP, 8-PIN MSOP, and 8-PIN SOIC
Packages
FUNCTIONAL DIAGRAM
DESCRIPTION
The X24C01 is a CMOS 1024 bit serial E2PROM,
internally organized as 128 x 8. The X24C01 features a
serial interface and software protocol allowing operation
on a simple two wire bus.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
(8) VCC
(4) VSS
(5) SDA
(6) SCL
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING
& CONTROL
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
XDEC
E2PROM
32 X 32
R/W
DOUT
ACK
PIN
YDEC
8
CK DATA REGISTER DOUT
3837 FHD F01
© Xicor, 1991 Patents Pending
3837-1.2 7/28/97 T1/C0/D0 SH
1 Characteristics subject to change without notice
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X24C01
WRITE OPERATIONS
Byte Write
To initiate a write operation, the master sends a start
condition followed by a seven bit word address and a write
bit. The X24C01 responds with an acknowledge, then
waits for eight bits of data and then responds with an
acknowledge. The master then terminates the transfer by
generating a stop condition, at which time the X24C01
begins the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress, the X24C01
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 4 for the
address, acknowledge and data transfer sequence.
Page Write
The most significant five bits of the word address define
the page address. The X24C01 is capable of a four byte
page write operation. It is initiated in the same manner as
the byte write operation, but instead of terminating the
transfer of data after the first data byte, the master can
transmit up to three more bytes. After the receipt of each
data byte, the X24C01 will respond with an acknowledge.
After the receipt of each data byte, the two low order
address bits are internally incremented by one. The high
order five bits of the address remain constant. If the
master should transmit more than four data bytes prior
to generating the stop condition, the address counter will
“roll over” and the previously transmitted data will be
overwritten. As with the byte write operation, all inputs
are disabled until completion of the internal write cycle.
Refer to Figure 5 for the address, acknowledge and data
transfer sequence.
Figure 4. Byte Write
BUS ACTIVITY:
SDA LINE
BUS ACTIVITY:
X24C01
S
T
A
R
WORD
ADDRESS
(n)
T
S
M LRA
S S/C
B BWK
DATA n
S
T
O
P
P
A
C
K
3837 FHD F09
Figure 5. Page Write
BUS ACTIVITY:
SDA LINE
BUS ACTIVITY:
X24C01
S
T
A
R
WORD
ADDRESS (n)
T
S
M LRA
S S/C
B BWK
DATA n
DATA n+1
AA
CC
KK
DATA n+3
S
T
O
P
P
A
C
K
3837 FHD F10
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for X24C01M-3.5 electronic component. |
| Information | Total 14 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ X24C01M-3.5.PDF Datasheet ] | |
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