X24320S8I-2.5 Datasheet PDF - Xicor
| Part Number | X24320S8I-2.5 | |
| Description | 400KHz 2-Wire Serial E2PROM with Block Lock | |
| Manufacturers | Xicor | |
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There is a preview and X24320S8I-2.5 download ( pdf file ) link at the bottom of this page. Total 17 Pages | ||
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32K
X24320
4K x 8 Bit
400KHz 2-Wire Serial E2PROM with Block LockTM
FEATURES
• Save Critical Data with Programmable
Block Lock Protection
—Block Lock (0, 1/4, 1/2, or all of E2PROM Array)
—Software Write Protection
—Programmable Hardware Write Protect
• In Circuit Programmable ROM Mode
• 400KHz 2-Wire Serial Interface
—Schmitt Trigger Input Noise Suppression
—Output Slope Control for Ground Bounce
Noise Elimination
• Longer Battery Life With Lower Power
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1µA
• 1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V
Power Supply Versions
• 32 Word Page Write Mode
—Minimizes Total Write Time Per Word
• Internally Organized 4K x 8
• Bidirectional Data Transfer Protocol
• Self-Timed Write Cycle
—Typical Write Cycle Time of 5ms
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
• 8-Lead SOIC
• 14-Lead TSSOP
• 8-Lead PDIP
FUNCTIONAL DIAGRAM
DESCRIPTION
The X24320 is a CMOS Serial E2PROM, internally
organized 4K x 8. The device features a serial inter-
face and software protocol allowing operation on a
simple two wire bus. The bus operates at 400 KHz all
the way down to 1.8V.
Three device select inputs (S0–S2) allow up to eight
devices to share a common two wire bus.
A Write Protect Register at the highest address loca-
tion, FFFFh, provides three write protection features:
Software Write Protect, Block Lock Protect, and
Programmable Hardware Write Protect. The Software
Write Protect feature prevents any nonvolatile writes to
the device until the WEL bit in the Write Protect
Register is set. The Block Lock Protection feature
gives the user four array block protect options, set by
programming two bits in the Write Protect Register.
The Programmable Hardware Write Protect feature
allows the user to install the device with WP tied to
VCC, write to and Block Lock the desired portions of
the memory array in circuit, and then enable the In
Circuit Programmable ROM Mode by programming the
WPEN bit HIGH in the Write Protect Register. After
this, the Block Locked portions of the array, including
the Write Protect Register itself, are permanently
protected from being erased.
SERIAL E2PROM DATA
AND ADDRESS (SDA)
DATA REGISTER
Y DECODE LOGIC
SCL
S2
S1
S0
COMMAND
DECODE
AND
CONTROL
LOGIC
BLOCK LOCK AND
WRITE PROTECT
CONTROL LOGIC
PAGE
DECODE
LOGIC
DEVICE
SELECT
LOGIC
WRITE
PROTECT
REGISTER
SERIAL E2PROM
ARRAY
4K x 8
1K x 8
1K x 8
2K x 8
WP
©Xicor, 1995, 1996 Patents Pending
7035-1.2 4/25/97 T0/C2/D0 SH
WRITE VOLTAGE
CONTROL
7035 FM 01
Characteristics subject to change without notice
1
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X24320
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits
of the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next 3 bits are the
device select bits S0, S1, and S2. This allows up to 8
devices to share a single bus. These bits are
compared to the S0, S1, and S2 device select input
pins. The last bit of the Slave Address Byte defines the
operation to be performed. When the R/W bit is a one,
then a read operation is selected. When it is zero then
a write operation is selected. Refer to figure 4. After
loading the Slave Address Byte from the SDA bus, the
device compares the device type bits with the value
“1010” and the device select bits with the status of the
device select input pins. If the compare is not successful,
no acknowledge is output during the ninth clock cycle
and the device returns to the standby mode.
The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the two Word
Address Bytes as shown in figure 4.
The internal organization of the E2 array is 128 pages by
32 bytes per page. The page address is partially
contained in the Word Address Byte 1 and partially in
bits 7 through 5 of the Word Address Byte 0. The byte
address is contained in bits 4 through 0 of the Word
Address Byte 0. See figure 4.
Figure 4. Device Addressing
DEVICE TYPE
IDENTIFIER
DEVICE
SELECT
1 0 1 0 S 2 S1 S0 R/ W
SLAVE ADDRESS BYTE
HIGH ORDER WORD ADDRESS
0 0 0 0 A11 A10 A9 A8
X24320 WORD ADDRESS BYTE 1
LOW ORDER WORD ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
WORD ADDRESS BYTE 0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
7035 FM 06
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for X24320S8I-2.5 electronic component. |
| Information | Total 17 Pages | |
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| Download | [ X24320S8I-2.5.PDF Datasheet ] | |
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