X24165VI-2.7 Datasheet PDF - Xicor
| Part Number | X24165VI-2.7 | |
| Description | Advanced 2-Wire Serial E2PROM with Block Lock Protection | |
| Manufacturers | Xicor | |
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Preliminary Information
16K
X24165
2048 x 8 Bit
Advanced 2-Wire Serial E2PROM with Block LockTM Protection
FEATURES
• 2.7V to 5.5V Power Supply
• Low Power CMOS
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1µA
• Internally Organized 2048 x 8
• New Programmable Block Lock Protection
—Software Write Protection
—Programmable Hardware Write Protect
• Block Lock (0, 1/4, 1/2, or all of the E2PROM
array)
• 2 Wire Serial Interface
• Bidirectional Data Transfer Protocol
• 32 Byte Page Write Mode
—Minimizes Total Write Time Per Byte
• Self Timed Write Cycle
—Typical Write Cycle Time of 5ms
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
• Available Packages
—8-Lead PDIP
—8-Lead SOIC (JEDEC)
—14-Lead TSSOP
DESCRIPTION
The X24165 is a CMOS 16,384 bit serial E2PROM,
internally organized 2048 x 8. The X24165 features a
serial interface and software protocol allowing opera-
tion on a simple two wire bus.
Three device select inputs (S0, S1, S2) allow up to
eight devices to share a common two wire bus.
A Write Protect Register at the highest address loca-
tion, 7FFh, provides three new write protection
features: Software Write Protect, Block Write Protect,
and Hardware Write Protect. The Software Write
Protect feature prevents any nonvolatile writes to the
X24165 until the WEL bit in the write protect register is
set. The Block Write Protection feature allows the user
to individually write protect four blocks of the array by
programming two bits in the write protect register. The
Programmable Hardware Write Protect feature allows
the user to install the X24165 with WP tied to VCC,
program the entire memory array in place, and then
enable the hardware write protection by programming
a WPEN bit in the write protect register. After this,
selected blocks of the array, including the write protect
register itself, are permanently write protected.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
FUNCTIONAL DIAGRAM
WP
VCC
VSS
SDA
START
STOP
LOGIC
START CYCLE
H.V. GENERATION
TIMING &
CONTROL
WRITE PROTECT
REGISTER AND
LOGIC
©Xicor, 1995, 1996 Patents Pending
6551-2.5 5/13/96 T1/C10/D0 NS
SCL
S2
S1
S0
SLAVE ADDRESS
REGISTER
+COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
R/W
DOUT
ACK
1
PIN
XDEC
E2PROM
64 X 256
YDEC
8
CK DATA REGISTER DOUT
6551 ILL F01.1
Characteristics subject to change without notice
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X24165
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing (see Figure 4). The
next three bits are the device select bits. A system
could have up to eight X24165’s on the bus. The eight
addresses are defined by the state of the S0, S1 and
S2 inputs. S1 of the slave address must be the inverse
of the S1 input pin.
Figure 4. Slave Address
DEVICE
TYPE
DEVICE
IDENTIFIER SELECT
HIGH ORDER
WORD
ADDRESS
1 S2 S1 S0 A10 A9 A8 R/W
6551 ILL F07.2
The next three bits of the slave address are an exten-
sion of the array’s address and are concatenated with
the eight bits of address in the word address field,
providing direct access to the whole 2048 x 8 array.
The last bit of the slave address defines the operation to
be performed. When set HIGH a read operation is
selected, when set LOW a write operation is selected.
Following the start condition, the X24165 monitors the
SDA bus comparing the slave address being transmitted
with its slave address device type identifier. Upon a
correct compare the X24165 outputs an acknowledge on
the SDA line. Depending on the state of the R/W bit, the
X24165 will execute a read or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24165 requires a second ad-
dress field. This address field is the word address, com-
prised of eight bits, providing access to any one of 2048
words in the array. Upon receipt of the word address, the
X24165 responds with an acknowledge and awaits the
next eight bits of data, again responding with an acknowl-
edge. The master then terminates the transfer by gener-
ating a stop condition, at which time the X24165 begins
the internal write cycle to the nonvolatile memory. While
the internal write cycle is in progress the X24165 inputs
are disabled, and the device will not respond to any re-
quests from the master. Refer to Figure 5 for the address,
acknowledge and data transfer sequence.
Figure 5. Byte Write
S
BUS ACTIVITY:
MASTER
T
A
R
SLAVE
ADDRESS
T
SDA LINE
S
BUS ACTIVITY:
X24165
WORD
ADDRESS
A
C
K
A
C
K
DATA
S
T
O
P
P
A
C
K
6551 ILL F08
5
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| Information | Total 17 Pages | |
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